1*b1d27b48SRoberto Vargas/* 2*b1d27b48SRoberto Vargas * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*b1d27b48SRoberto Vargas * 4*b1d27b48SRoberto Vargas * SPDX-License-Identifier: BSD-3-Clause 5*b1d27b48SRoberto Vargas */ 6*b1d27b48SRoberto Vargas 7*b1d27b48SRoberto Vargas#include <arch.h> 8*b1d27b48SRoberto Vargas#include <asm_macros.S> 9*b1d27b48SRoberto Vargas#include <bl_common.h> 10*b1d27b48SRoberto Vargas#include <el3_common_macros.S> 11*b1d27b48SRoberto Vargas 12*b1d27b48SRoberto Vargas .globl bl2_entrypoint 13*b1d27b48SRoberto Vargas .globl bl2_vector_table 14*b1d27b48SRoberto Vargas .globl bl2_el3_run_image 15*b1d27b48SRoberto Vargas .globl bl2_run_next_image 16*b1d27b48SRoberto Vargas 17*b1d27b48SRoberto Vargasfunc bl2_entrypoint 18*b1d27b48SRoberto Vargas /* Save arguments x0-x3 from previous Boot loader */ 19*b1d27b48SRoberto Vargas mov x20, x0 20*b1d27b48SRoberto Vargas mov x21, x1 21*b1d27b48SRoberto Vargas mov x22, x2 22*b1d27b48SRoberto Vargas mov x23, x3 23*b1d27b48SRoberto Vargas 24*b1d27b48SRoberto Vargas el3_entrypoint_common \ 25*b1d27b48SRoberto Vargas _init_sctlr=1 \ 26*b1d27b48SRoberto Vargas _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 27*b1d27b48SRoberto Vargas _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 28*b1d27b48SRoberto Vargas _init_memory=1 \ 29*b1d27b48SRoberto Vargas _init_c_runtime=1 \ 30*b1d27b48SRoberto Vargas _exception_vectors=bl2_el3_exceptions 31*b1d27b48SRoberto Vargas 32*b1d27b48SRoberto Vargas /* 33*b1d27b48SRoberto Vargas * Restore parameters of boot rom 34*b1d27b48SRoberto Vargas */ 35*b1d27b48SRoberto Vargas mov x0, x20 36*b1d27b48SRoberto Vargas mov x1, x21 37*b1d27b48SRoberto Vargas mov x2, x22 38*b1d27b48SRoberto Vargas mov x3, x23 39*b1d27b48SRoberto Vargas 40*b1d27b48SRoberto Vargas bl bl2_el3_early_platform_setup 41*b1d27b48SRoberto Vargas bl bl2_el3_plat_arch_setup 42*b1d27b48SRoberto Vargas 43*b1d27b48SRoberto Vargas /* --------------------------------------------- 44*b1d27b48SRoberto Vargas * Jump to main function. 45*b1d27b48SRoberto Vargas * --------------------------------------------- 46*b1d27b48SRoberto Vargas */ 47*b1d27b48SRoberto Vargas bl bl2_main 48*b1d27b48SRoberto Vargas 49*b1d27b48SRoberto Vargas /* --------------------------------------------- 50*b1d27b48SRoberto Vargas * Should never reach this point. 51*b1d27b48SRoberto Vargas * --------------------------------------------- 52*b1d27b48SRoberto Vargas */ 53*b1d27b48SRoberto Vargas no_ret plat_panic_handler 54*b1d27b48SRoberto Vargasendfunc bl2_entrypoint 55*b1d27b48SRoberto Vargas 56*b1d27b48SRoberto Vargasfunc bl2_run_next_image 57*b1d27b48SRoberto Vargas mov x20,x0 58*b1d27b48SRoberto Vargas /* 59*b1d27b48SRoberto Vargas * MMU needs to be disabled because both BL2 and BL31 execute 60*b1d27b48SRoberto Vargas * in EL3, and therefore share the same address space. 61*b1d27b48SRoberto Vargas * BL31 will initialize the address space according to its 62*b1d27b48SRoberto Vargas * own requirement. 63*b1d27b48SRoberto Vargas */ 64*b1d27b48SRoberto Vargas bl disable_mmu_icache_el3 65*b1d27b48SRoberto Vargas tlbi alle3 66*b1d27b48SRoberto Vargas bl bl2_el3_plat_prepare_exit 67*b1d27b48SRoberto Vargas 68*b1d27b48SRoberto Vargas ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 69*b1d27b48SRoberto Vargas msr elr_el3, x0 70*b1d27b48SRoberto Vargas msr spsr_el3, x1 71*b1d27b48SRoberto Vargas 72*b1d27b48SRoberto Vargas ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 73*b1d27b48SRoberto Vargas ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 74*b1d27b48SRoberto Vargas ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 75*b1d27b48SRoberto Vargas ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 76*b1d27b48SRoberto Vargas eret 77*b1d27b48SRoberto Vargasendfunc bl2_run_next_image 78