1b1d27b48SRoberto Vargas/* 2b1d27b48SRoberto Vargas * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3b1d27b48SRoberto Vargas * 4b1d27b48SRoberto Vargas * SPDX-License-Identifier: BSD-3-Clause 5b1d27b48SRoberto Vargas */ 6b1d27b48SRoberto Vargas 7b1d27b48SRoberto Vargas#include <arch.h> 8b1d27b48SRoberto Vargas#include <asm_macros.S> 9*09d40e0eSAntonio Nino Diaz#include <common/bl_common.h> 10b1d27b48SRoberto Vargas#include <el3_common_macros.S> 11b1d27b48SRoberto Vargas 12b1d27b48SRoberto Vargas .globl bl2_entrypoint 13b1d27b48SRoberto Vargas .globl bl2_vector_table 14b1d27b48SRoberto Vargas .globl bl2_el3_run_image 15b1d27b48SRoberto Vargas .globl bl2_run_next_image 16b1d27b48SRoberto Vargas 17b1d27b48SRoberto Vargasfunc bl2_entrypoint 18b1d27b48SRoberto Vargas /* Save arguments x0-x3 from previous Boot loader */ 19b1d27b48SRoberto Vargas mov x20, x0 20b1d27b48SRoberto Vargas mov x21, x1 21b1d27b48SRoberto Vargas mov x22, x2 22b1d27b48SRoberto Vargas mov x23, x3 23b1d27b48SRoberto Vargas 24b1d27b48SRoberto Vargas el3_entrypoint_common \ 25b1d27b48SRoberto Vargas _init_sctlr=1 \ 26b1d27b48SRoberto Vargas _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 27b1d27b48SRoberto Vargas _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 28b1d27b48SRoberto Vargas _init_memory=1 \ 29b1d27b48SRoberto Vargas _init_c_runtime=1 \ 30b1d27b48SRoberto Vargas _exception_vectors=bl2_el3_exceptions 31b1d27b48SRoberto Vargas 32b1d27b48SRoberto Vargas /* 33b1d27b48SRoberto Vargas * Restore parameters of boot rom 34b1d27b48SRoberto Vargas */ 35b1d27b48SRoberto Vargas mov x0, x20 36b1d27b48SRoberto Vargas mov x1, x21 37b1d27b48SRoberto Vargas mov x2, x22 38b1d27b48SRoberto Vargas mov x3, x23 39b1d27b48SRoberto Vargas 40b1d27b48SRoberto Vargas bl bl2_el3_early_platform_setup 41b1d27b48SRoberto Vargas bl bl2_el3_plat_arch_setup 42b1d27b48SRoberto Vargas 43b1d27b48SRoberto Vargas /* --------------------------------------------- 44b1d27b48SRoberto Vargas * Jump to main function. 45b1d27b48SRoberto Vargas * --------------------------------------------- 46b1d27b48SRoberto Vargas */ 47b1d27b48SRoberto Vargas bl bl2_main 48b1d27b48SRoberto Vargas 49b1d27b48SRoberto Vargas /* --------------------------------------------- 50b1d27b48SRoberto Vargas * Should never reach this point. 51b1d27b48SRoberto Vargas * --------------------------------------------- 52b1d27b48SRoberto Vargas */ 53b1d27b48SRoberto Vargas no_ret plat_panic_handler 54b1d27b48SRoberto Vargasendfunc bl2_entrypoint 55b1d27b48SRoberto Vargas 56b1d27b48SRoberto Vargasfunc bl2_run_next_image 57b1d27b48SRoberto Vargas mov x20,x0 58b1d27b48SRoberto Vargas /* 59b1d27b48SRoberto Vargas * MMU needs to be disabled because both BL2 and BL31 execute 60b1d27b48SRoberto Vargas * in EL3, and therefore share the same address space. 61b1d27b48SRoberto Vargas * BL31 will initialize the address space according to its 62b1d27b48SRoberto Vargas * own requirement. 63b1d27b48SRoberto Vargas */ 64b1d27b48SRoberto Vargas bl disable_mmu_icache_el3 65b1d27b48SRoberto Vargas tlbi alle3 66b1d27b48SRoberto Vargas bl bl2_el3_plat_prepare_exit 67b1d27b48SRoberto Vargas 68b1d27b48SRoberto Vargas ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 69b1d27b48SRoberto Vargas msr elr_el3, x0 70b1d27b48SRoberto Vargas msr spsr_el3, x1 71b1d27b48SRoberto Vargas 72b1d27b48SRoberto Vargas ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 73b1d27b48SRoberto Vargas ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 74b1d27b48SRoberto Vargas ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 75b1d27b48SRoberto Vargas ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 76b1d27b48SRoberto Vargas eret 77b1d27b48SRoberto Vargasendfunc bl2_run_next_image 78