1*6c09af9fSZelalem Aweke/* 2*6c09af9fSZelalem Aweke * Copyright (c) 2021, Arm Limited. All rights reserved. 3*6c09af9fSZelalem Aweke * 4*6c09af9fSZelalem Aweke * SPDX-License-Identifier: BSD-3-Clause 5*6c09af9fSZelalem Aweke */ 6*6c09af9fSZelalem Aweke 7*6c09af9fSZelalem Aweke#include <arch.h> 8*6c09af9fSZelalem Aweke#include <asm_macros.S> 9*6c09af9fSZelalem Aweke#include <common/bl_common.h> 10*6c09af9fSZelalem Aweke 11*6c09af9fSZelalem Aweke .globl bl2_run_next_image 12*6c09af9fSZelalem Aweke 13*6c09af9fSZelalem Aweke 14*6c09af9fSZelalem Awekefunc bl2_run_next_image 15*6c09af9fSZelalem Aweke mov r8,r0 16*6c09af9fSZelalem Aweke 17*6c09af9fSZelalem Aweke /* 18*6c09af9fSZelalem Aweke * MMU needs to be disabled because both BL2 and BL32 execute 19*6c09af9fSZelalem Aweke * in PL1, and therefore share the same address space. 20*6c09af9fSZelalem Aweke * BL32 will initialize the address space according to its 21*6c09af9fSZelalem Aweke * own requirement. 22*6c09af9fSZelalem Aweke */ 23*6c09af9fSZelalem Aweke bl disable_mmu_icache_secure 24*6c09af9fSZelalem Aweke stcopr r0, TLBIALL 25*6c09af9fSZelalem Aweke dsb sy 26*6c09af9fSZelalem Aweke isb 27*6c09af9fSZelalem Aweke mov r0, r8 28*6c09af9fSZelalem Aweke bl bl2_el3_plat_prepare_exit 29*6c09af9fSZelalem Aweke 30*6c09af9fSZelalem Aweke /* 31*6c09af9fSZelalem Aweke * Extract PC and SPSR based on struct `entry_point_info_t` 32*6c09af9fSZelalem Aweke * and load it in LR and SPSR registers respectively. 33*6c09af9fSZelalem Aweke */ 34*6c09af9fSZelalem Aweke ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET] 35*6c09af9fSZelalem Aweke ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] 36*6c09af9fSZelalem Aweke msr spsr_xc, r1 37*6c09af9fSZelalem Aweke 38*6c09af9fSZelalem Aweke /* Some BL32 stages expect lr_svc to provide the BL33 entry address */ 39*6c09af9fSZelalem Aweke cps #MODE32_svc 40*6c09af9fSZelalem Aweke ldr lr, [r8, #ENTRY_POINT_INFO_LR_SVC_OFFSET] 41*6c09af9fSZelalem Aweke cps #MODE32_mon 42*6c09af9fSZelalem Aweke 43*6c09af9fSZelalem Aweke add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET 44*6c09af9fSZelalem Aweke ldm r8, {r0, r1, r2, r3} 45*6c09af9fSZelalem Aweke exception_return 46*6c09af9fSZelalem Awekeendfunc bl2_run_next_image 47