1/* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl_common.h> 10 11 12 .globl bl2_vector_table 13 .globl bl2_entrypoint 14 15 16vector_base bl2_vector_table 17 b bl2_entrypoint 18 b report_exception /* Undef */ 19 b report_exception /* SVC call */ 20 b report_exception /* Prefetch abort */ 21 b report_exception /* Data abort */ 22 b report_exception /* Reserved */ 23 b report_exception /* IRQ */ 24 b report_exception /* FIQ */ 25 26 27func bl2_entrypoint 28 /*--------------------------------------------- 29 * Save arguments x0 - x3 from BL1 for future 30 * use. 31 * --------------------------------------------- 32 */ 33 mov r9, r0 34 mov r10, r1 35 mov r11, r2 36 mov r12, r3 37 38 /* --------------------------------------------- 39 * Set the exception vector to something sane. 40 * --------------------------------------------- 41 */ 42 ldr r0, =bl2_vector_table 43 stcopr r0, VBAR 44 isb 45 46 /* ----------------------------------------------------- 47 * Enable the instruction cache 48 * ----------------------------------------------------- 49 */ 50 ldcopr r0, SCTLR 51 orr r0, r0, #SCTLR_I_BIT 52 stcopr r0, SCTLR 53 isb 54 55 /* --------------------------------------------- 56 * Since BL2 executes after BL1, it is assumed 57 * here that BL1 has already has done the 58 * necessary register initializations. 59 * --------------------------------------------- 60 */ 61 62 /* --------------------------------------------- 63 * Invalidate the RW memory used by the BL2 64 * image. This includes the data and NOBITS 65 * sections. This is done to safeguard against 66 * possible corruption of this memory by dirty 67 * cache lines in a system cache as a result of 68 * use by an earlier boot loader stage. 69 * --------------------------------------------- 70 */ 71 ldr r0, =__RW_START__ 72 ldr r1, =__RW_END__ 73 sub r1, r1, r0 74 bl inv_dcache_range 75 76 /* --------------------------------------------- 77 * Zero out NOBITS sections. There are 2 of them: 78 * - the .bss section; 79 * - the coherent memory section. 80 * --------------------------------------------- 81 */ 82 ldr r0, =__BSS_START__ 83 ldr r1, =__BSS_SIZE__ 84 bl zeromem 85 86#if USE_COHERENT_MEM 87 ldr r0, =__COHERENT_RAM_START__ 88 ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ 89 bl zeromem 90#endif 91 92 /* -------------------------------------------- 93 * Allocate a stack whose memory will be marked 94 * as Normal-IS-WBWA when the MMU is enabled. 95 * There is no risk of reading stale stack 96 * memory after enabling the MMU as only the 97 * primary cpu is running at the moment. 98 * -------------------------------------------- 99 */ 100 bl plat_set_my_stack 101 102 /* --------------------------------------------- 103 * Initialize the stack protector canary before 104 * any C code is called. 105 * --------------------------------------------- 106 */ 107#if STACK_PROTECTOR_ENABLED 108 bl update_stack_protector_canary 109#endif 110 111 /* --------------------------------------------- 112 * Perform early platform setup & platform 113 * specific early arch. setup e.g. mmu setup 114 * --------------------------------------------- 115 */ 116 mov r0, r9 117 mov r1, r10 118 mov r2, r11 119 mov r3, r12 120 bl bl2_early_platform_setup2 121 bl bl2_plat_arch_setup 122 123 /* --------------------------------------------- 124 * Jump to main function. 125 * --------------------------------------------- 126 */ 127 bl bl2_main 128 129 /* --------------------------------------------- 130 * Should never reach this point. 131 * --------------------------------------------- 132 */ 133 no_ret plat_panic_handler 134 135endfunc bl2_entrypoint 136