1d48c12e9SYatharth Kochar/* 251faada7SDouglas Raillard * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3d48c12e9SYatharth Kochar * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5d48c12e9SYatharth Kochar */ 6d48c12e9SYatharth Kochar 7d48c12e9SYatharth Kochar#include <arch.h> 8d48c12e9SYatharth Kochar#include <asm_macros.S> 9d48c12e9SYatharth Kochar#include <bl_common.h> 10d48c12e9SYatharth Kochar 11d48c12e9SYatharth Kochar 12d48c12e9SYatharth Kochar .globl bl2_vector_table 13d48c12e9SYatharth Kochar .globl bl2_entrypoint 14d48c12e9SYatharth Kochar 15d48c12e9SYatharth Kochar 16d48c12e9SYatharth Kocharvector_base bl2_vector_table 17d48c12e9SYatharth Kochar b bl2_entrypoint 18d48c12e9SYatharth Kochar b report_exception /* Undef */ 19d48c12e9SYatharth Kochar b report_exception /* SVC call */ 20d48c12e9SYatharth Kochar b report_exception /* Prefetch abort */ 21d48c12e9SYatharth Kochar b report_exception /* Data abort */ 22d48c12e9SYatharth Kochar b report_exception /* Reserved */ 23d48c12e9SYatharth Kochar b report_exception /* IRQ */ 24d48c12e9SYatharth Kochar b report_exception /* FIQ */ 25d48c12e9SYatharth Kochar 26d48c12e9SYatharth Kochar 27d48c12e9SYatharth Kocharfunc bl2_entrypoint 28d48c12e9SYatharth Kochar /*--------------------------------------------- 29d48c12e9SYatharth Kochar * Save from r1 the extents of the trusted ram 30d48c12e9SYatharth Kochar * available to BL2 for future use. 31d48c12e9SYatharth Kochar * r0 is not currently used. 32d48c12e9SYatharth Kochar * --------------------------------------------- 33d48c12e9SYatharth Kochar */ 34d48c12e9SYatharth Kochar mov r11, r1 35d48c12e9SYatharth Kochar 36d48c12e9SYatharth Kochar /* --------------------------------------------- 37d48c12e9SYatharth Kochar * Set the exception vector to something sane. 38d48c12e9SYatharth Kochar * --------------------------------------------- 39d48c12e9SYatharth Kochar */ 40d48c12e9SYatharth Kochar ldr r0, =bl2_vector_table 41d48c12e9SYatharth Kochar stcopr r0, VBAR 42d48c12e9SYatharth Kochar isb 43d48c12e9SYatharth Kochar 44d48c12e9SYatharth Kochar /* ----------------------------------------------------- 45d48c12e9SYatharth Kochar * Enable the instruction cache 46d48c12e9SYatharth Kochar * ----------------------------------------------------- 47d48c12e9SYatharth Kochar */ 48d48c12e9SYatharth Kochar ldcopr r0, SCTLR 49d48c12e9SYatharth Kochar orr r0, r0, #SCTLR_I_BIT 50d48c12e9SYatharth Kochar stcopr r0, SCTLR 51d48c12e9SYatharth Kochar isb 52d48c12e9SYatharth Kochar 53d48c12e9SYatharth Kochar /* --------------------------------------------- 54d48c12e9SYatharth Kochar * Since BL2 executes after BL1, it is assumed 55d48c12e9SYatharth Kochar * here that BL1 has already has done the 56d48c12e9SYatharth Kochar * necessary register initializations. 57d48c12e9SYatharth Kochar * --------------------------------------------- 58d48c12e9SYatharth Kochar */ 59d48c12e9SYatharth Kochar 60d48c12e9SYatharth Kochar /* --------------------------------------------- 61d48c12e9SYatharth Kochar * Invalidate the RW memory used by the BL2 62d48c12e9SYatharth Kochar * image. This includes the data and NOBITS 63d48c12e9SYatharth Kochar * sections. This is done to safeguard against 64d48c12e9SYatharth Kochar * possible corruption of this memory by dirty 65d48c12e9SYatharth Kochar * cache lines in a system cache as a result of 66d48c12e9SYatharth Kochar * use by an earlier boot loader stage. 67d48c12e9SYatharth Kochar * --------------------------------------------- 68d48c12e9SYatharth Kochar */ 69d48c12e9SYatharth Kochar ldr r0, =__RW_START__ 70d48c12e9SYatharth Kochar ldr r1, =__RW_END__ 71d48c12e9SYatharth Kochar sub r1, r1, r0 72d48c12e9SYatharth Kochar bl inv_dcache_range 73d48c12e9SYatharth Kochar 74d48c12e9SYatharth Kochar /* --------------------------------------------- 75d48c12e9SYatharth Kochar * Zero out NOBITS sections. There are 2 of them: 76d48c12e9SYatharth Kochar * - the .bss section; 77d48c12e9SYatharth Kochar * - the coherent memory section. 78d48c12e9SYatharth Kochar * --------------------------------------------- 79d48c12e9SYatharth Kochar */ 80d48c12e9SYatharth Kochar ldr r0, =__BSS_START__ 81d48c12e9SYatharth Kochar ldr r1, =__BSS_SIZE__ 82d48c12e9SYatharth Kochar bl zeromem 83d48c12e9SYatharth Kochar 84d48c12e9SYatharth Kochar#if USE_COHERENT_MEM 85d48c12e9SYatharth Kochar ldr r0, =__COHERENT_RAM_START__ 86d48c12e9SYatharth Kochar ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ 87d48c12e9SYatharth Kochar bl zeromem 88d48c12e9SYatharth Kochar#endif 89d48c12e9SYatharth Kochar 90d48c12e9SYatharth Kochar /* -------------------------------------------- 91d48c12e9SYatharth Kochar * Allocate a stack whose memory will be marked 92d48c12e9SYatharth Kochar * as Normal-IS-WBWA when the MMU is enabled. 93d48c12e9SYatharth Kochar * There is no risk of reading stale stack 94d48c12e9SYatharth Kochar * memory after enabling the MMU as only the 95d48c12e9SYatharth Kochar * primary cpu is running at the moment. 96d48c12e9SYatharth Kochar * -------------------------------------------- 97d48c12e9SYatharth Kochar */ 98d48c12e9SYatharth Kochar bl plat_set_my_stack 99d48c12e9SYatharth Kochar 100d48c12e9SYatharth Kochar /* --------------------------------------------- 10151faada7SDouglas Raillard * Initialize the stack protector canary before 10251faada7SDouglas Raillard * any C code is called. 10351faada7SDouglas Raillard * --------------------------------------------- 10451faada7SDouglas Raillard */ 10551faada7SDouglas Raillard#if STACK_PROTECTOR_ENABLED 10651faada7SDouglas Raillard bl update_stack_protector_canary 10751faada7SDouglas Raillard#endif 10851faada7SDouglas Raillard 10951faada7SDouglas Raillard /* --------------------------------------------- 110d48c12e9SYatharth Kochar * Perform early platform setup & platform 111d48c12e9SYatharth Kochar * specific early arch. setup e.g. mmu setup 112d48c12e9SYatharth Kochar * --------------------------------------------- 113d48c12e9SYatharth Kochar */ 114d48c12e9SYatharth Kochar mov r0, r11 115d48c12e9SYatharth Kochar bl bl2_early_platform_setup 116d48c12e9SYatharth Kochar bl bl2_plat_arch_setup 117d48c12e9SYatharth Kochar 118d48c12e9SYatharth Kochar /* --------------------------------------------- 119d48c12e9SYatharth Kochar * Jump to main function. 120d48c12e9SYatharth Kochar * --------------------------------------------- 121d48c12e9SYatharth Kochar */ 122d48c12e9SYatharth Kochar bl bl2_main 123d48c12e9SYatharth Kochar 124d48c12e9SYatharth Kochar /* --------------------------------------------- 125d48c12e9SYatharth Kochar * Should never reach this point. 126d48c12e9SYatharth Kochar * --------------------------------------------- 127d48c12e9SYatharth Kochar */ 128a806dad5SJeenu Viswambharan no_ret plat_panic_handler 129d48c12e9SYatharth Kochar 130d48c12e9SYatharth Kocharendfunc bl2_entrypoint 131