1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <auth_mod.h> 11 #include <bl1.h> 12 #include <bl_common.h> 13 #include <console.h> 14 #include <debug.h> 15 #include <errata_report.h> 16 #include <platform.h> 17 #include <platform_def.h> 18 #include <smccc_helpers.h> 19 #include <utils.h> 20 #include <uuid.h> 21 #include "bl1_private.h" 22 23 /* BL1 Service UUID */ 24 DEFINE_SVC_UUID2(bl1_svc_uid, 25 0xd46739fd, 0xcb72, 0x9a4d, 0xb5, 0x75, 26 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a); 27 28 static void bl1_load_bl2(void); 29 30 /******************************************************************************* 31 * Helper utility to calculate the BL2 memory layout taking into consideration 32 * the BL1 RW data assuming that it is at the top of the memory layout. 33 ******************************************************************************/ 34 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 35 meminfo_t *bl2_mem_layout) 36 { 37 assert(bl1_mem_layout != NULL); 38 assert(bl2_mem_layout != NULL); 39 40 #if LOAD_IMAGE_V2 41 /* 42 * Remove BL1 RW data from the scope of memory visible to BL2. 43 * This is assuming BL1 RW data is at the top of bl1_mem_layout. 44 */ 45 assert(BL1_RW_BASE > bl1_mem_layout->total_base); 46 bl2_mem_layout->total_base = bl1_mem_layout->total_base; 47 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; 48 #else 49 /* Check that BL1's memory is lying outside of the free memory */ 50 assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) || 51 (BL1_RAM_BASE >= bl1_mem_layout->free_base + 52 bl1_mem_layout->free_size)); 53 54 /* Remove BL1 RW data from the scope of memory visible to BL2 */ 55 *bl2_mem_layout = *bl1_mem_layout; 56 reserve_mem(&bl2_mem_layout->total_base, 57 &bl2_mem_layout->total_size, 58 BL1_RAM_BASE, 59 BL1_RAM_LIMIT - BL1_RAM_BASE); 60 #endif /* LOAD_IMAGE_V2 */ 61 62 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); 63 } 64 65 #if !ERROR_DEPRECATED 66 /******************************************************************************* 67 * Compatibility default implementation for deprecated API. This has a weak 68 * definition. Platform specific code can override it if it wishes to. 69 ******************************************************************************/ 70 #pragma weak bl1_init_bl2_mem_layout 71 72 /******************************************************************************* 73 * Function that takes a memory layout into which BL2 has been loaded and 74 * populates a new memory layout for BL2 that ensures that BL1's data sections 75 * resident in secure RAM are not visible to BL2. 76 ******************************************************************************/ 77 void bl1_init_bl2_mem_layout(const struct meminfo *bl1_mem_layout, 78 struct meminfo *bl2_mem_layout) 79 { 80 bl1_calc_bl2_mem_layout(bl1_mem_layout, bl2_mem_layout); 81 } 82 #endif 83 84 /******************************************************************************* 85 * Function to perform late architectural and platform specific initialization. 86 * It also queries the platform to load and run next BL image. Only called 87 * by the primary cpu after a cold boot. 88 ******************************************************************************/ 89 void bl1_main(void) 90 { 91 unsigned int image_id; 92 93 /* Announce our arrival */ 94 NOTICE(FIRMWARE_WELCOME_STR); 95 NOTICE("BL1: %s\n", version_string); 96 NOTICE("BL1: %s\n", build_message); 97 98 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, 99 (void *)BL1_RAM_LIMIT); 100 101 print_errata_status(); 102 103 #if ENABLE_ASSERTIONS 104 u_register_t val; 105 /* 106 * Ensure that MMU/Caches and coherency are turned on 107 */ 108 #ifdef AARCH32 109 val = read_sctlr(); 110 #else 111 val = read_sctlr_el3(); 112 #endif 113 assert(val & SCTLR_M_BIT); 114 assert(val & SCTLR_C_BIT); 115 assert(val & SCTLR_I_BIT); 116 /* 117 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the 118 * provided platform value 119 */ 120 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; 121 /* 122 * If CWG is zero, then no CWG information is available but we can 123 * at least check the platform value is less than the architectural 124 * maximum. 125 */ 126 if (val != 0) 127 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); 128 else 129 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); 130 #endif /* ENABLE_ASSERTIONS */ 131 132 /* Perform remaining generic architectural setup from EL3 */ 133 bl1_arch_setup(); 134 135 #if TRUSTED_BOARD_BOOT 136 /* Initialize authentication module */ 137 auth_mod_init(); 138 #endif /* TRUSTED_BOARD_BOOT */ 139 140 /* Perform platform setup in BL1. */ 141 bl1_platform_setup(); 142 143 /* Get the image id of next image to load and run. */ 144 image_id = bl1_plat_get_next_image_id(); 145 146 /* 147 * We currently interpret any image id other than 148 * BL2_IMAGE_ID as the start of firmware update. 149 */ 150 if (image_id == BL2_IMAGE_ID) 151 bl1_load_bl2(); 152 else 153 NOTICE("BL1-FWU: *******FWU Process Started*******\n"); 154 155 bl1_prepare_next_image(image_id); 156 157 console_flush(); 158 } 159 160 /******************************************************************************* 161 * This function locates and loads the BL2 raw binary image in the trusted SRAM. 162 * Called by the primary cpu after a cold boot. 163 * TODO: Add support for alternative image load mechanism e.g using virtio/elf 164 * loader etc. 165 ******************************************************************************/ 166 static void bl1_load_bl2(void) 167 { 168 image_desc_t *image_desc; 169 image_info_t *image_info; 170 int err; 171 172 /* Get the image descriptor */ 173 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); 174 assert(image_desc); 175 176 /* Get the image info */ 177 image_info = &image_desc->image_info; 178 INFO("BL1: Loading BL2\n"); 179 180 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID); 181 if (err) { 182 ERROR("Failure in pre image load handling of BL2 (%d)\n", err); 183 plat_error_handler(err); 184 } 185 186 #if LOAD_IMAGE_V2 187 err = load_auth_image(BL2_IMAGE_ID, image_info); 188 #else 189 entry_point_info_t *ep_info; 190 meminfo_t *bl1_tzram_layout; 191 192 /* Get the entry point info */ 193 ep_info = &image_desc->ep_info; 194 195 /* Find out how much free trusted ram remains after BL1 load */ 196 bl1_tzram_layout = bl1_plat_sec_mem_layout(); 197 198 /* Load the BL2 image */ 199 err = load_auth_image(bl1_tzram_layout, 200 BL2_IMAGE_ID, 201 image_info->image_base, 202 image_info, 203 ep_info); 204 205 #endif /* LOAD_IMAGE_V2 */ 206 207 if (err) { 208 ERROR("Failed to load BL2 firmware.\n"); 209 plat_error_handler(err); 210 } 211 212 /* Allow platform to handle image information. */ 213 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID); 214 if (err) { 215 ERROR("Failure in post image load handling of BL2 (%d)\n", err); 216 plat_error_handler(err); 217 } 218 219 NOTICE("BL1: Booting BL2\n"); 220 } 221 222 /******************************************************************************* 223 * Function called just before handing over to the next BL to inform the user 224 * about the boot progress. In debug mode, also print details about the BL 225 * image's execution context. 226 ******************************************************************************/ 227 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info) 228 { 229 #ifdef AARCH32 230 NOTICE("BL1: Booting BL32\n"); 231 #else 232 NOTICE("BL1: Booting BL31\n"); 233 #endif /* AARCH32 */ 234 print_entry_point_info(bl_ep_info); 235 } 236 237 #if SPIN_ON_BL1_EXIT 238 void print_debug_loop_message(void) 239 { 240 NOTICE("BL1: Debug loop, spinning forever\n"); 241 NOTICE("BL1: Please connect the debugger to continue\n"); 242 } 243 #endif 244 245 /******************************************************************************* 246 * Top level handler for servicing BL1 SMCs. 247 ******************************************************************************/ 248 register_t bl1_smc_handler(unsigned int smc_fid, 249 register_t x1, 250 register_t x2, 251 register_t x3, 252 register_t x4, 253 void *cookie, 254 void *handle, 255 unsigned int flags) 256 { 257 258 #if TRUSTED_BOARD_BOOT 259 /* 260 * Dispatch FWU calls to FWU SMC handler and return its return 261 * value 262 */ 263 if (is_fwu_fid(smc_fid)) { 264 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie, 265 handle, flags); 266 } 267 #endif 268 269 switch (smc_fid) { 270 case BL1_SMC_CALL_COUNT: 271 SMC_RET1(handle, BL1_NUM_SMC_CALLS); 272 273 case BL1_SMC_UID: 274 SMC_UUID_RET(handle, bl1_svc_uid); 275 276 case BL1_SMC_VERSION: 277 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER); 278 279 default: 280 break; 281 } 282 283 WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid); 284 SMC_RET1(handle, SMC_UNK); 285 } 286 287 /******************************************************************************* 288 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI 289 * compliance when invoking bl1_smc_handler. 290 ******************************************************************************/ 291 register_t bl1_smc_wrapper(uint32_t smc_fid, 292 void *cookie, 293 void *handle, 294 unsigned int flags) 295 { 296 register_t x1, x2, x3, x4; 297 298 assert(handle); 299 300 get_smc_params_from_ctx(handle, x1, x2, x3, x4); 301 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 302 } 303