1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <auth_mod.h> 11 #include <bl1.h> 12 #include <bl_common.h> 13 #include <console.h> 14 #include <debug.h> 15 #include <errata_report.h> 16 #include <platform.h> 17 #include <platform_def.h> 18 #include <smccc_helpers.h> 19 #include <utils.h> 20 #include <uuid.h> 21 #include "bl1_private.h" 22 23 /* BL1 Service UUID */ 24 DEFINE_SVC_UUID2(bl1_svc_uid, 25 0xd46739fd, 0xcb72, 0x9a4d, 0xb5, 0x75, 26 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a); 27 28 static void bl1_load_bl2(void); 29 30 /******************************************************************************* 31 * Helper utility to calculate the BL2 memory layout taking into consideration 32 * the BL1 RW data assuming that it is at the top of the memory layout. 33 ******************************************************************************/ 34 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 35 meminfo_t *bl2_mem_layout) 36 { 37 assert(bl1_mem_layout != NULL); 38 assert(bl2_mem_layout != NULL); 39 40 /* 41 * Remove BL1 RW data from the scope of memory visible to BL2. 42 * This is assuming BL1 RW data is at the top of bl1_mem_layout. 43 */ 44 assert(BL1_RW_BASE > bl1_mem_layout->total_base); 45 bl2_mem_layout->total_base = bl1_mem_layout->total_base; 46 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; 47 48 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); 49 } 50 51 /******************************************************************************* 52 * Function to perform late architectural and platform specific initialization. 53 * It also queries the platform to load and run next BL image. Only called 54 * by the primary cpu after a cold boot. 55 ******************************************************************************/ 56 void bl1_main(void) 57 { 58 unsigned int image_id; 59 60 /* Announce our arrival */ 61 NOTICE(FIRMWARE_WELCOME_STR); 62 NOTICE("BL1: %s\n", version_string); 63 NOTICE("BL1: %s\n", build_message); 64 65 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, 66 (void *)BL1_RAM_LIMIT); 67 68 print_errata_status(); 69 70 #if ENABLE_ASSERTIONS 71 u_register_t val; 72 /* 73 * Ensure that MMU/Caches and coherency are turned on 74 */ 75 #ifdef AARCH32 76 val = read_sctlr(); 77 #else 78 val = read_sctlr_el3(); 79 #endif 80 assert(val & SCTLR_M_BIT); 81 assert(val & SCTLR_C_BIT); 82 assert(val & SCTLR_I_BIT); 83 /* 84 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the 85 * provided platform value 86 */ 87 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; 88 /* 89 * If CWG is zero, then no CWG information is available but we can 90 * at least check the platform value is less than the architectural 91 * maximum. 92 */ 93 if (val != 0) 94 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); 95 else 96 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); 97 #endif /* ENABLE_ASSERTIONS */ 98 99 /* Perform remaining generic architectural setup from EL3 */ 100 bl1_arch_setup(); 101 102 #if TRUSTED_BOARD_BOOT 103 /* Initialize authentication module */ 104 auth_mod_init(); 105 #endif /* TRUSTED_BOARD_BOOT */ 106 107 /* Perform platform setup in BL1. */ 108 bl1_platform_setup(); 109 110 /* Get the image id of next image to load and run. */ 111 image_id = bl1_plat_get_next_image_id(); 112 113 /* 114 * We currently interpret any image id other than 115 * BL2_IMAGE_ID as the start of firmware update. 116 */ 117 if (image_id == BL2_IMAGE_ID) 118 bl1_load_bl2(); 119 else 120 NOTICE("BL1-FWU: *******FWU Process Started*******\n"); 121 122 bl1_prepare_next_image(image_id); 123 124 console_flush(); 125 } 126 127 /******************************************************************************* 128 * This function locates and loads the BL2 raw binary image in the trusted SRAM. 129 * Called by the primary cpu after a cold boot. 130 * TODO: Add support for alternative image load mechanism e.g using virtio/elf 131 * loader etc. 132 ******************************************************************************/ 133 static void bl1_load_bl2(void) 134 { 135 image_desc_t *image_desc; 136 image_info_t *image_info; 137 int err; 138 139 /* Get the image descriptor */ 140 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); 141 assert(image_desc); 142 143 /* Get the image info */ 144 image_info = &image_desc->image_info; 145 INFO("BL1: Loading BL2\n"); 146 147 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID); 148 if (err) { 149 ERROR("Failure in pre image load handling of BL2 (%d)\n", err); 150 plat_error_handler(err); 151 } 152 153 err = load_auth_image(BL2_IMAGE_ID, image_info); 154 if (err) { 155 ERROR("Failed to load BL2 firmware.\n"); 156 plat_error_handler(err); 157 } 158 159 /* Allow platform to handle image information. */ 160 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID); 161 if (err) { 162 ERROR("Failure in post image load handling of BL2 (%d)\n", err); 163 plat_error_handler(err); 164 } 165 166 NOTICE("BL1: Booting BL2\n"); 167 } 168 169 /******************************************************************************* 170 * Function called just before handing over to the next BL to inform the user 171 * about the boot progress. In debug mode, also print details about the BL 172 * image's execution context. 173 ******************************************************************************/ 174 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info) 175 { 176 #ifdef AARCH32 177 NOTICE("BL1: Booting BL32\n"); 178 #else 179 NOTICE("BL1: Booting BL31\n"); 180 #endif /* AARCH32 */ 181 print_entry_point_info(bl_ep_info); 182 } 183 184 #if SPIN_ON_BL1_EXIT 185 void print_debug_loop_message(void) 186 { 187 NOTICE("BL1: Debug loop, spinning forever\n"); 188 NOTICE("BL1: Please connect the debugger to continue\n"); 189 } 190 #endif 191 192 /******************************************************************************* 193 * Top level handler for servicing BL1 SMCs. 194 ******************************************************************************/ 195 register_t bl1_smc_handler(unsigned int smc_fid, 196 register_t x1, 197 register_t x2, 198 register_t x3, 199 register_t x4, 200 void *cookie, 201 void *handle, 202 unsigned int flags) 203 { 204 205 #if TRUSTED_BOARD_BOOT 206 /* 207 * Dispatch FWU calls to FWU SMC handler and return its return 208 * value 209 */ 210 if (is_fwu_fid(smc_fid)) { 211 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie, 212 handle, flags); 213 } 214 #endif 215 216 switch (smc_fid) { 217 case BL1_SMC_CALL_COUNT: 218 SMC_RET1(handle, BL1_NUM_SMC_CALLS); 219 220 case BL1_SMC_UID: 221 SMC_UUID_RET(handle, bl1_svc_uid); 222 223 case BL1_SMC_VERSION: 224 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER); 225 226 default: 227 break; 228 } 229 230 WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid); 231 SMC_RET1(handle, SMC_UNK); 232 } 233 234 /******************************************************************************* 235 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI 236 * compliance when invoking bl1_smc_handler. 237 ******************************************************************************/ 238 register_t bl1_smc_wrapper(uint32_t smc_fid, 239 void *cookie, 240 void *handle, 241 unsigned int flags) 242 { 243 register_t x1, x2, x3, x4; 244 245 assert(handle); 246 247 get_smc_params_from_ctx(handle, x1, x2, x3, x4); 248 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 249 } 250