14f6ad66aSAchin Gupta /* 2e83b0cadSDan Handley * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 34f6ad66aSAchin Gupta * 44f6ad66aSAchin Gupta * Redistribution and use in source and binary forms, with or without 54f6ad66aSAchin Gupta * modification, are permitted provided that the following conditions are met: 64f6ad66aSAchin Gupta * 74f6ad66aSAchin Gupta * Redistributions of source code must retain the above copyright notice, this 84f6ad66aSAchin Gupta * list of conditions and the following disclaimer. 94f6ad66aSAchin Gupta * 104f6ad66aSAchin Gupta * Redistributions in binary form must reproduce the above copyright notice, 114f6ad66aSAchin Gupta * this list of conditions and the following disclaimer in the documentation 124f6ad66aSAchin Gupta * and/or other materials provided with the distribution. 134f6ad66aSAchin Gupta * 144f6ad66aSAchin Gupta * Neither the name of ARM nor the names of its contributors may be used 154f6ad66aSAchin Gupta * to endorse or promote products derived from this software without specific 164f6ad66aSAchin Gupta * prior written permission. 174f6ad66aSAchin Gupta * 184f6ad66aSAchin Gupta * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 194f6ad66aSAchin Gupta * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 204f6ad66aSAchin Gupta * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 214f6ad66aSAchin Gupta * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 224f6ad66aSAchin Gupta * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 234f6ad66aSAchin Gupta * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 244f6ad66aSAchin Gupta * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 254f6ad66aSAchin Gupta * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 264f6ad66aSAchin Gupta * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 274f6ad66aSAchin Gupta * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 284f6ad66aSAchin Gupta * POSSIBILITY OF SUCH DAMAGE. 294f6ad66aSAchin Gupta */ 304f6ad66aSAchin Gupta 3197043ac9SDan Handley #include <arch.h> 324f6ad66aSAchin Gupta #include <arch_helpers.h> 3397043ac9SDan Handley #include <assert.h> 3497043ac9SDan Handley #include <bl_common.h> 354112bfa0SVikram Kanigiri #include <debug.h> 3697043ac9SDan Handley #include <platform.h> 375f0cdb05SDan Handley #include <platform_def.h> 385b827a8fSDan Handley #include "bl1_private.h" 394f6ad66aSAchin Gupta 404f6ad66aSAchin Gupta /******************************************************************************* 4129fb905dSVikram Kanigiri * Runs BL2 from the given entry point. It results in dropping the 4229fb905dSVikram Kanigiri * exception level 4329fb905dSVikram Kanigiri ******************************************************************************/ 444112bfa0SVikram Kanigiri static void __dead2 bl1_run_bl2(entry_point_info_t *bl2_ep) 4529fb905dSVikram Kanigiri { 4629fb905dSVikram Kanigiri bl1_arch_next_el_setup(); 4729fb905dSVikram Kanigiri 4829fb905dSVikram Kanigiri /* Tell next EL what we want done */ 4929fb905dSVikram Kanigiri bl2_ep->args.arg0 = RUN_IMAGE; 5029fb905dSVikram Kanigiri 514112bfa0SVikram Kanigiri if (GET_SECURITY_STATE(bl2_ep->h.attr) == NON_SECURE) 524112bfa0SVikram Kanigiri change_security_state(GET_SECURITY_STATE(bl2_ep->h.attr)); 5329fb905dSVikram Kanigiri 5429fb905dSVikram Kanigiri write_spsr_el3(bl2_ep->spsr); 554112bfa0SVikram Kanigiri write_elr_el3(bl2_ep->pc); 5629fb905dSVikram Kanigiri 5729fb905dSVikram Kanigiri eret(bl2_ep->args.arg0, 5829fb905dSVikram Kanigiri bl2_ep->args.arg1, 5929fb905dSVikram Kanigiri bl2_ep->args.arg2, 6029fb905dSVikram Kanigiri bl2_ep->args.arg3, 6129fb905dSVikram Kanigiri bl2_ep->args.arg4, 6229fb905dSVikram Kanigiri bl2_ep->args.arg5, 6329fb905dSVikram Kanigiri bl2_ep->args.arg6, 6429fb905dSVikram Kanigiri bl2_ep->args.arg7); 6529fb905dSVikram Kanigiri } 6629fb905dSVikram Kanigiri 678f55dfb4SSandrine Bailleux /******************************************************************************* 688f55dfb4SSandrine Bailleux * The next function has a weak definition. Platform specific code can override 698f55dfb4SSandrine Bailleux * it if it wishes to. 708f55dfb4SSandrine Bailleux ******************************************************************************/ 718f55dfb4SSandrine Bailleux #pragma weak bl1_init_bl2_mem_layout 728f55dfb4SSandrine Bailleux 738f55dfb4SSandrine Bailleux /******************************************************************************* 748f55dfb4SSandrine Bailleux * Function that takes a memory layout into which BL2 has been loaded and 758f55dfb4SSandrine Bailleux * populates a new memory layout for BL2 that ensures that BL1's data sections 768f55dfb4SSandrine Bailleux * resident in secure RAM are not visible to BL2. 778f55dfb4SSandrine Bailleux ******************************************************************************/ 788f55dfb4SSandrine Bailleux void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 798f55dfb4SSandrine Bailleux meminfo_t *bl2_mem_layout) 808f55dfb4SSandrine Bailleux { 818f55dfb4SSandrine Bailleux const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; 828f55dfb4SSandrine Bailleux 838f55dfb4SSandrine Bailleux assert(bl1_mem_layout != NULL); 848f55dfb4SSandrine Bailleux assert(bl2_mem_layout != NULL); 858f55dfb4SSandrine Bailleux 868f55dfb4SSandrine Bailleux /* Check that BL1's memory is lying outside of the free memory */ 878f55dfb4SSandrine Bailleux assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) || 888f55dfb4SSandrine Bailleux (BL1_RAM_BASE >= bl1_mem_layout->free_base + bl1_mem_layout->free_size)); 898f55dfb4SSandrine Bailleux 908f55dfb4SSandrine Bailleux /* Remove BL1 RW data from the scope of memory visible to BL2 */ 918f55dfb4SSandrine Bailleux *bl2_mem_layout = *bl1_mem_layout; 928f55dfb4SSandrine Bailleux reserve_mem(&bl2_mem_layout->total_base, 938f55dfb4SSandrine Bailleux &bl2_mem_layout->total_size, 948f55dfb4SSandrine Bailleux BL1_RAM_BASE, 958f55dfb4SSandrine Bailleux bl1_size); 968f55dfb4SSandrine Bailleux 978f55dfb4SSandrine Bailleux flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); 988f55dfb4SSandrine Bailleux } 9929fb905dSVikram Kanigiri 10029fb905dSVikram Kanigiri /******************************************************************************* 1014f6ad66aSAchin Gupta * Function to perform late architectural and platform specific initialization. 1024f6ad66aSAchin Gupta * It also locates and loads the BL2 raw binary image in the trusted DRAM. Only 1034f6ad66aSAchin Gupta * called by the primary cpu after a cold boot. 1044f6ad66aSAchin Gupta * TODO: Add support for alternative image load mechanism e.g using virtio/elf 1054f6ad66aSAchin Gupta * loader etc. 1064f6ad66aSAchin Gupta ******************************************************************************/ 1074f6ad66aSAchin Gupta void bl1_main(void) 1084f6ad66aSAchin Gupta { 109*6ad2e461SDan Handley /* Announce our arrival */ 110*6ad2e461SDan Handley NOTICE(FIRMWARE_WELCOME_STR); 111*6ad2e461SDan Handley NOTICE("BL1: %s\n", version_string); 112*6ad2e461SDan Handley NOTICE("BL1: %s\n", build_message); 113*6ad2e461SDan Handley 114*6ad2e461SDan Handley INFO("BL1: RAM 0x%lx - 0x%lx\n", BL1_RAM_BASE, BL1_RAM_LIMIT); 115*6ad2e461SDan Handley 11640a6f647SJames Morrissey #if DEBUG 1176ba0b6d6SVikram Kanigiri unsigned long sctlr_el3 = read_sctlr_el3(); 11840a6f647SJames Morrissey #endif 1194112bfa0SVikram Kanigiri image_info_t bl2_image_info = { {0} }; 1204112bfa0SVikram Kanigiri entry_point_info_t bl2_ep = { {0} }; 121fb037bfbSDan Handley meminfo_t *bl1_tzram_layout; 122fb037bfbSDan Handley meminfo_t *bl2_tzram_layout = 0x0; 1234112bfa0SVikram Kanigiri int err; 1244f6ad66aSAchin Gupta 1254f6ad66aSAchin Gupta /* 1264f6ad66aSAchin Gupta * Ensure that MMU/Caches and coherency are turned on 1274f6ad66aSAchin Gupta */ 1284f6ad66aSAchin Gupta assert(sctlr_el3 | SCTLR_M_BIT); 1294f6ad66aSAchin Gupta assert(sctlr_el3 | SCTLR_C_BIT); 1304f6ad66aSAchin Gupta assert(sctlr_el3 | SCTLR_I_BIT); 1314f6ad66aSAchin Gupta 1324f6ad66aSAchin Gupta /* Perform remaining generic architectural setup from EL3 */ 1334f6ad66aSAchin Gupta bl1_arch_setup(); 1344f6ad66aSAchin Gupta 1354f6ad66aSAchin Gupta /* Perform platform setup in BL1. */ 1364f6ad66aSAchin Gupta bl1_platform_setup(); 1374f6ad66aSAchin Gupta 1384112bfa0SVikram Kanigiri SET_PARAM_HEAD(&bl2_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0); 1394112bfa0SVikram Kanigiri SET_PARAM_HEAD(&bl2_ep, PARAM_EP, VERSION_1, 0); 1404112bfa0SVikram Kanigiri 1418f55dfb4SSandrine Bailleux /* Find out how much free trusted ram remains after BL1 load */ 142ee12f6f7SSandrine Bailleux bl1_tzram_layout = bl1_plat_sec_mem_layout(); 1438f55dfb4SSandrine Bailleux 1448f55dfb4SSandrine Bailleux /* Load the BL2 image */ 1454112bfa0SVikram Kanigiri err = load_image(bl1_tzram_layout, 1468f55dfb4SSandrine Bailleux BL2_IMAGE_NAME, 1474112bfa0SVikram Kanigiri BL2_BASE, 1484112bfa0SVikram Kanigiri &bl2_image_info, 1494112bfa0SVikram Kanigiri &bl2_ep); 1504112bfa0SVikram Kanigiri if (err) { 1514112bfa0SVikram Kanigiri /* 1524112bfa0SVikram Kanigiri * TODO: print failure to load BL2 but also add a tzwdog timer 1534112bfa0SVikram Kanigiri * which will reset the system eventually. 1544112bfa0SVikram Kanigiri */ 155*6ad2e461SDan Handley ERROR("Failed to load BL2 firmware.\n"); 1564112bfa0SVikram Kanigiri panic(); 1574112bfa0SVikram Kanigiri } 1584f6ad66aSAchin Gupta /* 1594f6ad66aSAchin Gupta * Create a new layout of memory for BL2 as seen by BL1 i.e. 1604f6ad66aSAchin Gupta * tell it the amount of total and free memory available. 1614f6ad66aSAchin Gupta * This layout is created at the first free address visible 1624f6ad66aSAchin Gupta * to BL2. BL2 will read the memory layout before using its 1634f6ad66aSAchin Gupta * memory for other purposes. 1644f6ad66aSAchin Gupta */ 165fb037bfbSDan Handley bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base; 1668f55dfb4SSandrine Bailleux bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout); 1674f6ad66aSAchin Gupta 1684112bfa0SVikram Kanigiri bl1_plat_set_bl2_ep_info(&bl2_image_info, &bl2_ep); 16929fb905dSVikram Kanigiri bl2_ep.args.arg1 = (unsigned long)bl2_tzram_layout; 170*6ad2e461SDan Handley NOTICE("BL1: Booting BL2\n"); 171*6ad2e461SDan Handley INFO("BL1: BL2 address = 0x%llx\n", 1724112bfa0SVikram Kanigiri (unsigned long long) bl2_ep.pc); 173*6ad2e461SDan Handley INFO("BL1: BL2 spsr = 0x%x\n", bl2_ep.spsr); 174*6ad2e461SDan Handley VERBOSE("BL1: BL2 memory layout address = 0x%llx\n", 1754f6ad66aSAchin Gupta (unsigned long long) bl2_tzram_layout); 176*6ad2e461SDan Handley 17729fb905dSVikram Kanigiri bl1_run_bl2(&bl2_ep); 1784f6ad66aSAchin Gupta 1794f6ad66aSAchin Gupta return; 1804f6ad66aSAchin Gupta } 1814f6ad66aSAchin Gupta 1824f6ad66aSAchin Gupta /******************************************************************************* 1834f6ad66aSAchin Gupta * Temporary function to print the fact that BL2 has done its job and BL31 is 1844f6ad66aSAchin Gupta * about to be loaded. This is needed as long as printfs cannot be used 1854f6ad66aSAchin Gupta ******************************************************************************/ 1864112bfa0SVikram Kanigiri void display_boot_progress(entry_point_info_t *bl31_ep_info) 1874f6ad66aSAchin Gupta { 188*6ad2e461SDan Handley NOTICE("BL1: Booting BL3-1\n"); 189*6ad2e461SDan Handley INFO("BL1: BL3-1 address = 0x%llx\n", 190*6ad2e461SDan Handley (unsigned long long)bl31_ep_info->pc); 191*6ad2e461SDan Handley INFO("BL1: BL3-1 spsr = 0x%llx\n", 192*6ad2e461SDan Handley (unsigned long long)bl31_ep_info->spsr); 193*6ad2e461SDan Handley INFO("BL1: BL3-1 params address = 0x%llx\n", 19429fb905dSVikram Kanigiri (unsigned long long)bl31_ep_info->args.arg0); 195*6ad2e461SDan Handley INFO("BL1: BL3-1 plat params address = 0x%llx\n", 1964112bfa0SVikram Kanigiri (unsigned long long)bl31_ep_info->args.arg1); 1974f6ad66aSAchin Gupta } 198