xref: /rk3399_ARM-atf/bl1/bl1_main.c (revision 4112bfa0c223eda73af1cfe57ca7dc926f767dd8)
14f6ad66aSAchin Gupta /*
2e83b0cadSDan Handley  * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
34f6ad66aSAchin Gupta  *
44f6ad66aSAchin Gupta  * Redistribution and use in source and binary forms, with or without
54f6ad66aSAchin Gupta  * modification, are permitted provided that the following conditions are met:
64f6ad66aSAchin Gupta  *
74f6ad66aSAchin Gupta  * Redistributions of source code must retain the above copyright notice, this
84f6ad66aSAchin Gupta  * list of conditions and the following disclaimer.
94f6ad66aSAchin Gupta  *
104f6ad66aSAchin Gupta  * Redistributions in binary form must reproduce the above copyright notice,
114f6ad66aSAchin Gupta  * this list of conditions and the following disclaimer in the documentation
124f6ad66aSAchin Gupta  * and/or other materials provided with the distribution.
134f6ad66aSAchin Gupta  *
144f6ad66aSAchin Gupta  * Neither the name of ARM nor the names of its contributors may be used
154f6ad66aSAchin Gupta  * to endorse or promote products derived from this software without specific
164f6ad66aSAchin Gupta  * prior written permission.
174f6ad66aSAchin Gupta  *
184f6ad66aSAchin Gupta  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
194f6ad66aSAchin Gupta  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
204f6ad66aSAchin Gupta  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
214f6ad66aSAchin Gupta  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
224f6ad66aSAchin Gupta  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
234f6ad66aSAchin Gupta  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
244f6ad66aSAchin Gupta  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
254f6ad66aSAchin Gupta  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
264f6ad66aSAchin Gupta  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
274f6ad66aSAchin Gupta  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
284f6ad66aSAchin Gupta  * POSSIBILITY OF SUCH DAMAGE.
294f6ad66aSAchin Gupta  */
304f6ad66aSAchin Gupta 
3197043ac9SDan Handley #include <arch.h>
324f6ad66aSAchin Gupta #include <arch_helpers.h>
3397043ac9SDan Handley #include <assert.h>
3497043ac9SDan Handley #include <bl_common.h>
354f6ad66aSAchin Gupta #include <bl1.h>
36*4112bfa0SVikram Kanigiri #include <debug.h>
3797043ac9SDan Handley #include <platform.h>
3897043ac9SDan Handley #include <stdio.h>
395b827a8fSDan Handley #include "bl1_private.h"
404f6ad66aSAchin Gupta 
414f6ad66aSAchin Gupta /*******************************************************************************
4229fb905dSVikram Kanigiri  * Runs BL2 from the given entry point. It results in dropping the
4329fb905dSVikram Kanigiri  * exception level
4429fb905dSVikram Kanigiri  ******************************************************************************/
45*4112bfa0SVikram Kanigiri static void __dead2 bl1_run_bl2(entry_point_info_t *bl2_ep)
4629fb905dSVikram Kanigiri {
4729fb905dSVikram Kanigiri 	bl1_arch_next_el_setup();
4829fb905dSVikram Kanigiri 
4929fb905dSVikram Kanigiri 	/* Tell next EL what we want done */
5029fb905dSVikram Kanigiri 	bl2_ep->args.arg0 = RUN_IMAGE;
5129fb905dSVikram Kanigiri 
52*4112bfa0SVikram Kanigiri 	if (GET_SECURITY_STATE(bl2_ep->h.attr) == NON_SECURE)
53*4112bfa0SVikram Kanigiri 		change_security_state(GET_SECURITY_STATE(bl2_ep->h.attr));
5429fb905dSVikram Kanigiri 
5529fb905dSVikram Kanigiri 	write_spsr_el3(bl2_ep->spsr);
56*4112bfa0SVikram Kanigiri 	write_elr_el3(bl2_ep->pc);
5729fb905dSVikram Kanigiri 
5829fb905dSVikram Kanigiri 	eret(bl2_ep->args.arg0,
5929fb905dSVikram Kanigiri 		bl2_ep->args.arg1,
6029fb905dSVikram Kanigiri 		bl2_ep->args.arg2,
6129fb905dSVikram Kanigiri 		bl2_ep->args.arg3,
6229fb905dSVikram Kanigiri 		bl2_ep->args.arg4,
6329fb905dSVikram Kanigiri 		bl2_ep->args.arg5,
6429fb905dSVikram Kanigiri 		bl2_ep->args.arg6,
6529fb905dSVikram Kanigiri 		bl2_ep->args.arg7);
6629fb905dSVikram Kanigiri }
6729fb905dSVikram Kanigiri 
6829fb905dSVikram Kanigiri 
6929fb905dSVikram Kanigiri /*******************************************************************************
704f6ad66aSAchin Gupta  * Function to perform late architectural and platform specific initialization.
714f6ad66aSAchin Gupta  * It also locates and loads the BL2 raw binary image in the trusted DRAM. Only
724f6ad66aSAchin Gupta  * called by the primary cpu after a cold boot.
734f6ad66aSAchin Gupta  * TODO: Add support for alternative image load mechanism e.g using virtio/elf
744f6ad66aSAchin Gupta  * loader etc.
754f6ad66aSAchin Gupta   ******************************************************************************/
764f6ad66aSAchin Gupta void bl1_main(void)
774f6ad66aSAchin Gupta {
7840a6f647SJames Morrissey #if DEBUG
796ba0b6d6SVikram Kanigiri 	unsigned long sctlr_el3 = read_sctlr_el3();
8040a6f647SJames Morrissey #endif
8129fb905dSVikram Kanigiri 	unsigned int load_type = TOP_LOAD;
82*4112bfa0SVikram Kanigiri 	image_info_t bl2_image_info = { {0} };
83*4112bfa0SVikram Kanigiri 	entry_point_info_t bl2_ep = { {0} };
84fb037bfbSDan Handley 	meminfo_t *bl1_tzram_layout;
85fb037bfbSDan Handley 	meminfo_t *bl2_tzram_layout = 0x0;
86*4112bfa0SVikram Kanigiri 	int err;
874f6ad66aSAchin Gupta 
884f6ad66aSAchin Gupta 	/*
894f6ad66aSAchin Gupta 	 * Ensure that MMU/Caches and coherency are turned on
904f6ad66aSAchin Gupta 	 */
914f6ad66aSAchin Gupta 	assert(sctlr_el3 | SCTLR_M_BIT);
924f6ad66aSAchin Gupta 	assert(sctlr_el3 | SCTLR_C_BIT);
934f6ad66aSAchin Gupta 	assert(sctlr_el3 | SCTLR_I_BIT);
944f6ad66aSAchin Gupta 
954f6ad66aSAchin Gupta 	/* Perform remaining generic architectural setup from EL3 */
964f6ad66aSAchin Gupta 	bl1_arch_setup();
974f6ad66aSAchin Gupta 
984f6ad66aSAchin Gupta 	/* Perform platform setup in BL1. */
994f6ad66aSAchin Gupta 	bl1_platform_setup();
1004f6ad66aSAchin Gupta 
1014f6ad66aSAchin Gupta 	/* Announce our arrival */
1024f6ad66aSAchin Gupta 	printf(FIRMWARE_WELCOME_STR);
103fb052462SJon Medhurst 	printf("%s\n\r", build_message);
1044f6ad66aSAchin Gupta 
105*4112bfa0SVikram Kanigiri 	SET_PARAM_HEAD(&bl2_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0);
106*4112bfa0SVikram Kanigiri 	SET_PARAM_HEAD(&bl2_ep, PARAM_EP, VERSION_1, 0);
107*4112bfa0SVikram Kanigiri 
1084f6ad66aSAchin Gupta 	/*
1094f6ad66aSAchin Gupta 	 * Find out how much free trusted ram remains after BL1 load
1104f6ad66aSAchin Gupta 	 * & load the BL2 image at its top
1114f6ad66aSAchin Gupta 	 */
112ee12f6f7SSandrine Bailleux 	bl1_tzram_layout = bl1_plat_sec_mem_layout();
113*4112bfa0SVikram Kanigiri 	err = load_image(bl1_tzram_layout,
1144f6ad66aSAchin Gupta 			      (const char *) BL2_IMAGE_NAME,
115*4112bfa0SVikram Kanigiri 			      load_type,
116*4112bfa0SVikram Kanigiri 			      BL2_BASE,
117*4112bfa0SVikram Kanigiri 			      &bl2_image_info,
118*4112bfa0SVikram Kanigiri 			      &bl2_ep);
119*4112bfa0SVikram Kanigiri 	if (err) {
120*4112bfa0SVikram Kanigiri 		/*
121*4112bfa0SVikram Kanigiri 		 * TODO: print failure to load BL2 but also add a tzwdog timer
122*4112bfa0SVikram Kanigiri 		 * which will reset the system eventually.
123*4112bfa0SVikram Kanigiri 		 */
124*4112bfa0SVikram Kanigiri 		printf("Failed to load boot loader stage 2 (BL2) firmware.\n");
125*4112bfa0SVikram Kanigiri 		panic();
126*4112bfa0SVikram Kanigiri 	}
1274f6ad66aSAchin Gupta 	/*
1284f6ad66aSAchin Gupta 	 * Create a new layout of memory for BL2 as seen by BL1 i.e.
1294f6ad66aSAchin Gupta 	 * tell it the amount of total and free memory available.
1304f6ad66aSAchin Gupta 	 * This layout is created at the first free address visible
1314f6ad66aSAchin Gupta 	 * to BL2. BL2 will read the memory layout before using its
1324f6ad66aSAchin Gupta 	 * memory for other purposes.
1334f6ad66aSAchin Gupta 	 */
134fb037bfbSDan Handley 	bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base;
135ee12f6f7SSandrine Bailleux 	init_bl2_mem_layout(bl1_tzram_layout,
1364f6ad66aSAchin Gupta 			    bl2_tzram_layout,
1374f6ad66aSAchin Gupta 			    load_type,
138*4112bfa0SVikram Kanigiri 			    bl2_image_info.image_base);
1394f6ad66aSAchin Gupta 
140*4112bfa0SVikram Kanigiri 	bl1_plat_set_bl2_ep_info(&bl2_image_info, &bl2_ep);
14129fb905dSVikram Kanigiri 	bl2_ep.args.arg1 = (unsigned long)bl2_tzram_layout;
142*4112bfa0SVikram Kanigiri 	printf("Booting trusted firmware boot loader stage 2\n");
1434f6ad66aSAchin Gupta #if DEBUG
144*4112bfa0SVikram Kanigiri 	printf("BL2 address = 0x%llx\n",
145*4112bfa0SVikram Kanigiri 		(unsigned long long) bl2_ep.pc);
146*4112bfa0SVikram Kanigiri 	printf("BL2 cpsr = 0x%x\n", bl2_ep.spsr);
147*4112bfa0SVikram Kanigiri 	printf("BL2 memory layout address = 0x%llx\n",
1484f6ad66aSAchin Gupta 	       (unsigned long long) bl2_tzram_layout);
1494f6ad66aSAchin Gupta #endif
15029fb905dSVikram Kanigiri 	bl1_run_bl2(&bl2_ep);
1514f6ad66aSAchin Gupta 
1524f6ad66aSAchin Gupta 	return;
1534f6ad66aSAchin Gupta }
1544f6ad66aSAchin Gupta 
1554f6ad66aSAchin Gupta /*******************************************************************************
1564f6ad66aSAchin Gupta  * Temporary function to print the fact that BL2 has done its job and BL31 is
1574f6ad66aSAchin Gupta  * about to be loaded. This is needed as long as printfs cannot be used
1584f6ad66aSAchin Gupta  ******************************************************************************/
159*4112bfa0SVikram Kanigiri void display_boot_progress(entry_point_info_t *bl31_ep_info)
1604f6ad66aSAchin Gupta {
1614f6ad66aSAchin Gupta 	printf("Booting trusted firmware boot loader stage 3\n\r");
1624f6ad66aSAchin Gupta #if DEBUG
163*4112bfa0SVikram Kanigiri 	printf("BL31 address = 0x%llx\n", (unsigned long long)bl31_ep_info->pc);
164*4112bfa0SVikram Kanigiri 	printf("BL31 cpsr = 0x%llx\n", (unsigned long long)bl31_ep_info->spsr);
165*4112bfa0SVikram Kanigiri 	printf("BL31 params address = 0x%llx\n",
16629fb905dSVikram Kanigiri 			(unsigned long long)bl31_ep_info->args.arg0);
167*4112bfa0SVikram Kanigiri 	printf("BL31 plat params address = 0x%llx\n",
168*4112bfa0SVikram Kanigiri 			(unsigned long long)bl31_ep_info->args.arg1);
1694f6ad66aSAchin Gupta #endif
1704f6ad66aSAchin Gupta 	return;
1714f6ad66aSAchin Gupta }
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