xref: /rk3399_ARM-atf/bl1/bl1_main.c (revision 29fb905d5f36a415a170a4bffeadf13b5f084345)
14f6ad66aSAchin Gupta /*
2e83b0cadSDan Handley  * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
34f6ad66aSAchin Gupta  *
44f6ad66aSAchin Gupta  * Redistribution and use in source and binary forms, with or without
54f6ad66aSAchin Gupta  * modification, are permitted provided that the following conditions are met:
64f6ad66aSAchin Gupta  *
74f6ad66aSAchin Gupta  * Redistributions of source code must retain the above copyright notice, this
84f6ad66aSAchin Gupta  * list of conditions and the following disclaimer.
94f6ad66aSAchin Gupta  *
104f6ad66aSAchin Gupta  * Redistributions in binary form must reproduce the above copyright notice,
114f6ad66aSAchin Gupta  * this list of conditions and the following disclaimer in the documentation
124f6ad66aSAchin Gupta  * and/or other materials provided with the distribution.
134f6ad66aSAchin Gupta  *
144f6ad66aSAchin Gupta  * Neither the name of ARM nor the names of its contributors may be used
154f6ad66aSAchin Gupta  * to endorse or promote products derived from this software without specific
164f6ad66aSAchin Gupta  * prior written permission.
174f6ad66aSAchin Gupta  *
184f6ad66aSAchin Gupta  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
194f6ad66aSAchin Gupta  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
204f6ad66aSAchin Gupta  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
214f6ad66aSAchin Gupta  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
224f6ad66aSAchin Gupta  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
234f6ad66aSAchin Gupta  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
244f6ad66aSAchin Gupta  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
254f6ad66aSAchin Gupta  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
264f6ad66aSAchin Gupta  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
274f6ad66aSAchin Gupta  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
284f6ad66aSAchin Gupta  * POSSIBILITY OF SUCH DAMAGE.
294f6ad66aSAchin Gupta  */
304f6ad66aSAchin Gupta 
3197043ac9SDan Handley #include <arch.h>
324f6ad66aSAchin Gupta #include <arch_helpers.h>
3397043ac9SDan Handley #include <assert.h>
3497043ac9SDan Handley #include <bl_common.h>
354f6ad66aSAchin Gupta #include <bl1.h>
3697043ac9SDan Handley #include <platform.h>
3797043ac9SDan Handley #include <stdio.h>
385b827a8fSDan Handley #include "bl1_private.h"
394f6ad66aSAchin Gupta 
404f6ad66aSAchin Gupta /*******************************************************************************
41*29fb905dSVikram Kanigiri  * Runs BL2 from the given entry point. It results in dropping the
42*29fb905dSVikram Kanigiri  * exception level
43*29fb905dSVikram Kanigiri  ******************************************************************************/
44*29fb905dSVikram Kanigiri static void __dead2 bl1_run_bl2(el_change_info_t *bl2_ep)
45*29fb905dSVikram Kanigiri {
46*29fb905dSVikram Kanigiri 	bl1_arch_next_el_setup();
47*29fb905dSVikram Kanigiri 
48*29fb905dSVikram Kanigiri 	/* Tell next EL what we want done */
49*29fb905dSVikram Kanigiri 	bl2_ep->args.arg0 = RUN_IMAGE;
50*29fb905dSVikram Kanigiri 
51*29fb905dSVikram Kanigiri 	if (bl2_ep->security_state == NON_SECURE)
52*29fb905dSVikram Kanigiri 		change_security_state(bl2_ep->security_state);
53*29fb905dSVikram Kanigiri 
54*29fb905dSVikram Kanigiri 	write_spsr_el3(bl2_ep->spsr);
55*29fb905dSVikram Kanigiri 	write_elr_el3(bl2_ep->entrypoint);
56*29fb905dSVikram Kanigiri 
57*29fb905dSVikram Kanigiri 	eret(bl2_ep->args.arg0,
58*29fb905dSVikram Kanigiri 		bl2_ep->args.arg1,
59*29fb905dSVikram Kanigiri 		bl2_ep->args.arg2,
60*29fb905dSVikram Kanigiri 		bl2_ep->args.arg3,
61*29fb905dSVikram Kanigiri 		bl2_ep->args.arg4,
62*29fb905dSVikram Kanigiri 		bl2_ep->args.arg5,
63*29fb905dSVikram Kanigiri 		bl2_ep->args.arg6,
64*29fb905dSVikram Kanigiri 		bl2_ep->args.arg7);
65*29fb905dSVikram Kanigiri }
66*29fb905dSVikram Kanigiri 
67*29fb905dSVikram Kanigiri 
68*29fb905dSVikram Kanigiri /*******************************************************************************
694f6ad66aSAchin Gupta  * Function to perform late architectural and platform specific initialization.
704f6ad66aSAchin Gupta  * It also locates and loads the BL2 raw binary image in the trusted DRAM. Only
714f6ad66aSAchin Gupta  * called by the primary cpu after a cold boot.
724f6ad66aSAchin Gupta  * TODO: Add support for alternative image load mechanism e.g using virtio/elf
734f6ad66aSAchin Gupta  * loader etc.
744f6ad66aSAchin Gupta   ******************************************************************************/
754f6ad66aSAchin Gupta void bl1_main(void)
764f6ad66aSAchin Gupta {
7740a6f647SJames Morrissey #if DEBUG
786ba0b6d6SVikram Kanigiri 	unsigned long sctlr_el3 = read_sctlr_el3();
7940a6f647SJames Morrissey #endif
804f6ad66aSAchin Gupta 	unsigned long bl2_base;
81*29fb905dSVikram Kanigiri 	unsigned int load_type = TOP_LOAD;
82fb037bfbSDan Handley 	meminfo_t *bl1_tzram_layout;
83fb037bfbSDan Handley 	meminfo_t *bl2_tzram_layout = 0x0;
84*29fb905dSVikram Kanigiri 	el_change_info_t bl2_ep = {0};
854f6ad66aSAchin Gupta 
864f6ad66aSAchin Gupta 	/*
874f6ad66aSAchin Gupta 	 * Ensure that MMU/Caches and coherency are turned on
884f6ad66aSAchin Gupta 	 */
894f6ad66aSAchin Gupta 	assert(sctlr_el3 | SCTLR_M_BIT);
904f6ad66aSAchin Gupta 	assert(sctlr_el3 | SCTLR_C_BIT);
914f6ad66aSAchin Gupta 	assert(sctlr_el3 | SCTLR_I_BIT);
924f6ad66aSAchin Gupta 
934f6ad66aSAchin Gupta 	/* Perform remaining generic architectural setup from EL3 */
944f6ad66aSAchin Gupta 	bl1_arch_setup();
954f6ad66aSAchin Gupta 
964f6ad66aSAchin Gupta 	/* Perform platform setup in BL1. */
974f6ad66aSAchin Gupta 	bl1_platform_setup();
984f6ad66aSAchin Gupta 
994f6ad66aSAchin Gupta 	/* Announce our arrival */
1004f6ad66aSAchin Gupta 	printf(FIRMWARE_WELCOME_STR);
101fb052462SJon Medhurst 	printf("%s\n\r", build_message);
1024f6ad66aSAchin Gupta 
1034f6ad66aSAchin Gupta 	/*
1044f6ad66aSAchin Gupta 	 * Find out how much free trusted ram remains after BL1 load
1054f6ad66aSAchin Gupta 	 * & load the BL2 image at its top
1064f6ad66aSAchin Gupta 	 */
107ee12f6f7SSandrine Bailleux 	bl1_tzram_layout = bl1_plat_sec_mem_layout();
108ee12f6f7SSandrine Bailleux 	bl2_base = load_image(bl1_tzram_layout,
1094f6ad66aSAchin Gupta 			      (const char *) BL2_IMAGE_NAME,
1104f6ad66aSAchin Gupta 			      load_type, BL2_BASE);
1114f6ad66aSAchin Gupta 
1124f6ad66aSAchin Gupta 	/*
1134f6ad66aSAchin Gupta 	 * Create a new layout of memory for BL2 as seen by BL1 i.e.
1144f6ad66aSAchin Gupta 	 * tell it the amount of total and free memory available.
1154f6ad66aSAchin Gupta 	 * This layout is created at the first free address visible
1164f6ad66aSAchin Gupta 	 * to BL2. BL2 will read the memory layout before using its
1174f6ad66aSAchin Gupta 	 * memory for other purposes.
1184f6ad66aSAchin Gupta 	 */
119fb037bfbSDan Handley 	bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base;
120ee12f6f7SSandrine Bailleux 	init_bl2_mem_layout(bl1_tzram_layout,
1214f6ad66aSAchin Gupta 			    bl2_tzram_layout,
1224f6ad66aSAchin Gupta 			    load_type,
1234f6ad66aSAchin Gupta 			    bl2_base);
1244f6ad66aSAchin Gupta 
1254f6ad66aSAchin Gupta 	if (bl2_base) {
126*29fb905dSVikram Kanigiri 		bl2_ep.spsr =
127*29fb905dSVikram Kanigiri 			SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
128*29fb905dSVikram Kanigiri 		bl2_ep.entrypoint = bl2_base;
129*29fb905dSVikram Kanigiri 		bl2_ep.security_state = SECURE;
130*29fb905dSVikram Kanigiri 		bl2_ep.args.arg1 = (unsigned long)bl2_tzram_layout;
1314f6ad66aSAchin Gupta 		printf("Booting trusted firmware boot loader stage 2\n\r");
1324f6ad66aSAchin Gupta #if DEBUG
1334f6ad66aSAchin Gupta 		printf("BL2 address = 0x%llx \n\r", (unsigned long long) bl2_base);
134*29fb905dSVikram Kanigiri 		printf("BL2 cpsr = 0x%x \n\r", bl2_ep.spsr);
1354f6ad66aSAchin Gupta 		printf("BL2 memory layout address = 0x%llx \n\r",
1364f6ad66aSAchin Gupta 		       (unsigned long long) bl2_tzram_layout);
1374f6ad66aSAchin Gupta #endif
138*29fb905dSVikram Kanigiri 		bl1_run_bl2(&bl2_ep);
1394f6ad66aSAchin Gupta 	}
1404f6ad66aSAchin Gupta 
1414f6ad66aSAchin Gupta 	/*
1424f6ad66aSAchin Gupta 	 * TODO: print failure to load BL2 but also add a tzwdog timer
1434f6ad66aSAchin Gupta 	 * which will reset the system eventually.
1444f6ad66aSAchin Gupta 	 */
1454f6ad66aSAchin Gupta 	printf("Failed to load boot loader stage 2 (BL2) firmware.\n\r");
1464f6ad66aSAchin Gupta 	return;
1474f6ad66aSAchin Gupta }
1484f6ad66aSAchin Gupta 
1494f6ad66aSAchin Gupta /*******************************************************************************
1504f6ad66aSAchin Gupta  * Temporary function to print the fact that BL2 has done its job and BL31 is
1514f6ad66aSAchin Gupta  * about to be loaded. This is needed as long as printfs cannot be used
1524f6ad66aSAchin Gupta  ******************************************************************************/
153*29fb905dSVikram Kanigiri void display_boot_progress(el_change_info_t *bl31_ep_info)
1544f6ad66aSAchin Gupta {
1554f6ad66aSAchin Gupta 	printf("Booting trusted firmware boot loader stage 3\n\r");
1564f6ad66aSAchin Gupta #if DEBUG
157*29fb905dSVikram Kanigiri 	printf("BL31 address = 0x%llx\n",
158*29fb905dSVikram Kanigiri 			(unsigned long long)bl31_ep_info->entrypoint);
159*29fb905dSVikram Kanigiri 	printf("BL31 cpsr = 0x%llx\n",
160*29fb905dSVikram Kanigiri 			(unsigned long long)bl31_ep_info->spsr);
161*29fb905dSVikram Kanigiri 	printf("BL31 args address = 0x%llx\n",
162*29fb905dSVikram Kanigiri 			(unsigned long long)bl31_ep_info->args.arg0);
1634f6ad66aSAchin Gupta #endif
1644f6ad66aSAchin Gupta 	return;
1654f6ad66aSAchin Gupta }
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