xref: /rk3399_ARM-atf/bl1/bl1_main.c (revision 1779ba6b97fbff87290f164c7c78559329173e02)
14f6ad66aSAchin Gupta /*
2ce4c820dSDan Handley  * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
34f6ad66aSAchin Gupta  *
44f6ad66aSAchin Gupta  * Redistribution and use in source and binary forms, with or without
54f6ad66aSAchin Gupta  * modification, are permitted provided that the following conditions are met:
64f6ad66aSAchin Gupta  *
74f6ad66aSAchin Gupta  * Redistributions of source code must retain the above copyright notice, this
84f6ad66aSAchin Gupta  * list of conditions and the following disclaimer.
94f6ad66aSAchin Gupta  *
104f6ad66aSAchin Gupta  * Redistributions in binary form must reproduce the above copyright notice,
114f6ad66aSAchin Gupta  * this list of conditions and the following disclaimer in the documentation
124f6ad66aSAchin Gupta  * and/or other materials provided with the distribution.
134f6ad66aSAchin Gupta  *
144f6ad66aSAchin Gupta  * Neither the name of ARM nor the names of its contributors may be used
154f6ad66aSAchin Gupta  * to endorse or promote products derived from this software without specific
164f6ad66aSAchin Gupta  * prior written permission.
174f6ad66aSAchin Gupta  *
184f6ad66aSAchin Gupta  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
194f6ad66aSAchin Gupta  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
204f6ad66aSAchin Gupta  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
214f6ad66aSAchin Gupta  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
224f6ad66aSAchin Gupta  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
234f6ad66aSAchin Gupta  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
244f6ad66aSAchin Gupta  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
254f6ad66aSAchin Gupta  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
264f6ad66aSAchin Gupta  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
274f6ad66aSAchin Gupta  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
284f6ad66aSAchin Gupta  * POSSIBILITY OF SUCH DAMAGE.
294f6ad66aSAchin Gupta  */
304f6ad66aSAchin Gupta 
3197043ac9SDan Handley #include <arch.h>
324f6ad66aSAchin Gupta #include <arch_helpers.h>
3397043ac9SDan Handley #include <assert.h>
34*1779ba6bSJuan Castillo #include <auth_mod.h>
3597043ac9SDan Handley #include <bl_common.h>
364112bfa0SVikram Kanigiri #include <debug.h>
3797043ac9SDan Handley #include <platform.h>
385f0cdb05SDan Handley #include <platform_def.h>
395b827a8fSDan Handley #include "bl1_private.h"
404f6ad66aSAchin Gupta 
414f6ad66aSAchin Gupta /*******************************************************************************
4229fb905dSVikram Kanigiri  * Runs BL2 from the given entry point. It results in dropping the
4329fb905dSVikram Kanigiri  * exception level
4429fb905dSVikram Kanigiri  ******************************************************************************/
454112bfa0SVikram Kanigiri static void __dead2 bl1_run_bl2(entry_point_info_t *bl2_ep)
4629fb905dSVikram Kanigiri {
4729fb905dSVikram Kanigiri 	bl1_arch_next_el_setup();
4829fb905dSVikram Kanigiri 
4929fb905dSVikram Kanigiri 	/* Tell next EL what we want done */
5029fb905dSVikram Kanigiri 	bl2_ep->args.arg0 = RUN_IMAGE;
5129fb905dSVikram Kanigiri 
524112bfa0SVikram Kanigiri 	if (GET_SECURITY_STATE(bl2_ep->h.attr) == NON_SECURE)
534112bfa0SVikram Kanigiri 		change_security_state(GET_SECURITY_STATE(bl2_ep->h.attr));
5429fb905dSVikram Kanigiri 
5529fb905dSVikram Kanigiri 	write_spsr_el3(bl2_ep->spsr);
564112bfa0SVikram Kanigiri 	write_elr_el3(bl2_ep->pc);
5729fb905dSVikram Kanigiri 
5829fb905dSVikram Kanigiri 	eret(bl2_ep->args.arg0,
5929fb905dSVikram Kanigiri 		bl2_ep->args.arg1,
6029fb905dSVikram Kanigiri 		bl2_ep->args.arg2,
6129fb905dSVikram Kanigiri 		bl2_ep->args.arg3,
6229fb905dSVikram Kanigiri 		bl2_ep->args.arg4,
6329fb905dSVikram Kanigiri 		bl2_ep->args.arg5,
6429fb905dSVikram Kanigiri 		bl2_ep->args.arg6,
6529fb905dSVikram Kanigiri 		bl2_ep->args.arg7);
6629fb905dSVikram Kanigiri }
6729fb905dSVikram Kanigiri 
688f55dfb4SSandrine Bailleux /*******************************************************************************
698f55dfb4SSandrine Bailleux  * The next function has a weak definition. Platform specific code can override
708f55dfb4SSandrine Bailleux  * it if it wishes to.
718f55dfb4SSandrine Bailleux  ******************************************************************************/
728f55dfb4SSandrine Bailleux #pragma weak bl1_init_bl2_mem_layout
738f55dfb4SSandrine Bailleux 
748f55dfb4SSandrine Bailleux /*******************************************************************************
758f55dfb4SSandrine Bailleux  * Function that takes a memory layout into which BL2 has been loaded and
768f55dfb4SSandrine Bailleux  * populates a new memory layout for BL2 that ensures that BL1's data sections
778f55dfb4SSandrine Bailleux  * resident in secure RAM are not visible to BL2.
788f55dfb4SSandrine Bailleux  ******************************************************************************/
798f55dfb4SSandrine Bailleux void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
808f55dfb4SSandrine Bailleux 			     meminfo_t *bl2_mem_layout)
818f55dfb4SSandrine Bailleux {
828f55dfb4SSandrine Bailleux 	const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
838f55dfb4SSandrine Bailleux 
848f55dfb4SSandrine Bailleux 	assert(bl1_mem_layout != NULL);
858f55dfb4SSandrine Bailleux 	assert(bl2_mem_layout != NULL);
868f55dfb4SSandrine Bailleux 
878f55dfb4SSandrine Bailleux 	/* Check that BL1's memory is lying outside of the free memory */
888f55dfb4SSandrine Bailleux 	assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) ||
898f55dfb4SSandrine Bailleux 	       (BL1_RAM_BASE >= bl1_mem_layout->free_base + bl1_mem_layout->free_size));
908f55dfb4SSandrine Bailleux 
918f55dfb4SSandrine Bailleux 	/* Remove BL1 RW data from the scope of memory visible to BL2 */
928f55dfb4SSandrine Bailleux 	*bl2_mem_layout = *bl1_mem_layout;
938f55dfb4SSandrine Bailleux 	reserve_mem(&bl2_mem_layout->total_base,
948f55dfb4SSandrine Bailleux 		    &bl2_mem_layout->total_size,
958f55dfb4SSandrine Bailleux 		    BL1_RAM_BASE,
968f55dfb4SSandrine Bailleux 		    bl1_size);
978f55dfb4SSandrine Bailleux 
988f55dfb4SSandrine Bailleux 	flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
998f55dfb4SSandrine Bailleux }
10029fb905dSVikram Kanigiri 
10129fb905dSVikram Kanigiri /*******************************************************************************
1024f6ad66aSAchin Gupta  * Function to perform late architectural and platform specific initialization.
1034f6ad66aSAchin Gupta  * It also locates and loads the BL2 raw binary image in the trusted DRAM. Only
1044f6ad66aSAchin Gupta  * called by the primary cpu after a cold boot.
1054f6ad66aSAchin Gupta  * TODO: Add support for alternative image load mechanism e.g using virtio/elf
1064f6ad66aSAchin Gupta  * loader etc.
1074f6ad66aSAchin Gupta   ******************************************************************************/
1084f6ad66aSAchin Gupta void bl1_main(void)
1094f6ad66aSAchin Gupta {
1106ad2e461SDan Handley 	/* Announce our arrival */
1116ad2e461SDan Handley 	NOTICE(FIRMWARE_WELCOME_STR);
1126ad2e461SDan Handley 	NOTICE("BL1: %s\n", version_string);
1136ad2e461SDan Handley 	NOTICE("BL1: %s\n", build_message);
1146ad2e461SDan Handley 
1156ad2e461SDan Handley 	INFO("BL1: RAM 0x%lx - 0x%lx\n", BL1_RAM_BASE, BL1_RAM_LIMIT);
1166ad2e461SDan Handley 
1174112bfa0SVikram Kanigiri 	image_info_t bl2_image_info = { {0} };
1184112bfa0SVikram Kanigiri 	entry_point_info_t bl2_ep = { {0} };
119fb037bfbSDan Handley 	meminfo_t *bl1_tzram_layout;
120fb037bfbSDan Handley 	meminfo_t *bl2_tzram_layout = 0x0;
1214112bfa0SVikram Kanigiri 	int err;
1224f6ad66aSAchin Gupta 
123ce4c820dSDan Handley #if DEBUG
124ce4c820dSDan Handley 	unsigned long val;
1254f6ad66aSAchin Gupta 	/*
1264f6ad66aSAchin Gupta 	 * Ensure that MMU/Caches and coherency are turned on
1274f6ad66aSAchin Gupta 	 */
128ce4c820dSDan Handley 	val = read_sctlr_el3();
129354ab57dSAndrew Thoelke 	assert(val & SCTLR_M_BIT);
130354ab57dSAndrew Thoelke 	assert(val & SCTLR_C_BIT);
131354ab57dSAndrew Thoelke 	assert(val & SCTLR_I_BIT);
132ce4c820dSDan Handley 	/*
133ce4c820dSDan Handley 	 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
134ce4c820dSDan Handley 	 * provided platform value
135ce4c820dSDan Handley 	 */
136ce4c820dSDan Handley 	val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
137ce4c820dSDan Handley 	/*
138ce4c820dSDan Handley 	 * If CWG is zero, then no CWG information is available but we can
139ce4c820dSDan Handley 	 * at least check the platform value is less than the architectural
140ce4c820dSDan Handley 	 * maximum.
141ce4c820dSDan Handley 	 */
142ce4c820dSDan Handley 	if (val != 0)
143ce4c820dSDan Handley 		assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
144ce4c820dSDan Handley 	else
145ce4c820dSDan Handley 		assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
146ce4c820dSDan Handley #endif
1474f6ad66aSAchin Gupta 
1484f6ad66aSAchin Gupta 	/* Perform remaining generic architectural setup from EL3 */
1494f6ad66aSAchin Gupta 	bl1_arch_setup();
1504f6ad66aSAchin Gupta 
1514f6ad66aSAchin Gupta 	/* Perform platform setup in BL1. */
1524f6ad66aSAchin Gupta 	bl1_platform_setup();
1534f6ad66aSAchin Gupta 
1544112bfa0SVikram Kanigiri 	SET_PARAM_HEAD(&bl2_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0);
1554112bfa0SVikram Kanigiri 	SET_PARAM_HEAD(&bl2_ep, PARAM_EP, VERSION_1, 0);
1564112bfa0SVikram Kanigiri 
1578f55dfb4SSandrine Bailleux 	/* Find out how much free trusted ram remains after BL1 load */
158ee12f6f7SSandrine Bailleux 	bl1_tzram_layout = bl1_plat_sec_mem_layout();
1598f55dfb4SSandrine Bailleux 
16016948ae1SJuan Castillo 	INFO("BL1: Loading BL2\n");
16116948ae1SJuan Castillo 
16201df3c14SJuan Castillo #if TRUSTED_BOARD_BOOT
16301df3c14SJuan Castillo 	/* Initialize authentication module */
164*1779ba6bSJuan Castillo 	auth_mod_init();
16501df3c14SJuan Castillo #endif /* TRUSTED_BOARD_BOOT */
16601df3c14SJuan Castillo 
1678f55dfb4SSandrine Bailleux 	/* Load the BL2 image */
168*1779ba6bSJuan Castillo 	err = load_auth_image(bl1_tzram_layout,
16916948ae1SJuan Castillo 			 BL2_IMAGE_ID,
1704112bfa0SVikram Kanigiri 			 BL2_BASE,
1714112bfa0SVikram Kanigiri 			 &bl2_image_info,
1724112bfa0SVikram Kanigiri 			 &bl2_ep);
173*1779ba6bSJuan Castillo 
1744112bfa0SVikram Kanigiri 	if (err) {
1754112bfa0SVikram Kanigiri 		/*
1764112bfa0SVikram Kanigiri 		 * TODO: print failure to load BL2 but also add a tzwdog timer
1774112bfa0SVikram Kanigiri 		 * which will reset the system eventually.
1784112bfa0SVikram Kanigiri 		 */
1796ad2e461SDan Handley 		ERROR("Failed to load BL2 firmware.\n");
1804112bfa0SVikram Kanigiri 		panic();
1814112bfa0SVikram Kanigiri 	}
18201df3c14SJuan Castillo 
1834f6ad66aSAchin Gupta 	/*
1844f6ad66aSAchin Gupta 	 * Create a new layout of memory for BL2 as seen by BL1 i.e.
1854f6ad66aSAchin Gupta 	 * tell it the amount of total and free memory available.
1864f6ad66aSAchin Gupta 	 * This layout is created at the first free address visible
1874f6ad66aSAchin Gupta 	 * to BL2. BL2 will read the memory layout before using its
1884f6ad66aSAchin Gupta 	 * memory for other purposes.
1894f6ad66aSAchin Gupta 	 */
190fb037bfbSDan Handley 	bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base;
1918f55dfb4SSandrine Bailleux 	bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
1924f6ad66aSAchin Gupta 
1934112bfa0SVikram Kanigiri 	bl1_plat_set_bl2_ep_info(&bl2_image_info, &bl2_ep);
19429fb905dSVikram Kanigiri 	bl2_ep.args.arg1 = (unsigned long)bl2_tzram_layout;
1956ad2e461SDan Handley 	NOTICE("BL1: Booting BL2\n");
1966ad2e461SDan Handley 	INFO("BL1: BL2 address = 0x%llx\n",
1974112bfa0SVikram Kanigiri 		(unsigned long long) bl2_ep.pc);
1986ad2e461SDan Handley 	INFO("BL1: BL2 spsr = 0x%x\n", bl2_ep.spsr);
1996ad2e461SDan Handley 	VERBOSE("BL1: BL2 memory layout address = 0x%llx\n",
2004f6ad66aSAchin Gupta 		(unsigned long long) bl2_tzram_layout);
2016ad2e461SDan Handley 
20229fb905dSVikram Kanigiri 	bl1_run_bl2(&bl2_ep);
2034f6ad66aSAchin Gupta 
2044f6ad66aSAchin Gupta 	return;
2054f6ad66aSAchin Gupta }
2064f6ad66aSAchin Gupta 
2074f6ad66aSAchin Gupta /*******************************************************************************
2084f6ad66aSAchin Gupta  * Temporary function to print the fact that BL2 has done its job and BL31 is
2094f6ad66aSAchin Gupta  * about to be loaded. This is needed as long as printfs cannot be used
2104f6ad66aSAchin Gupta  ******************************************************************************/
2114112bfa0SVikram Kanigiri void display_boot_progress(entry_point_info_t *bl31_ep_info)
2124f6ad66aSAchin Gupta {
2136ad2e461SDan Handley 	NOTICE("BL1: Booting BL3-1\n");
2146ad2e461SDan Handley 	INFO("BL1: BL3-1 address = 0x%llx\n",
2156ad2e461SDan Handley 		(unsigned long long)bl31_ep_info->pc);
2166ad2e461SDan Handley 	INFO("BL1: BL3-1 spsr = 0x%llx\n",
2176ad2e461SDan Handley 		(unsigned long long)bl31_ep_info->spsr);
2186ad2e461SDan Handley 	INFO("BL1: BL3-1 params address = 0x%llx\n",
21929fb905dSVikram Kanigiri 		(unsigned long long)bl31_ep_info->args.arg0);
2206ad2e461SDan Handley 	INFO("BL1: BL3-1 plat params address = 0x%llx\n",
2214112bfa0SVikram Kanigiri 		(unsigned long long)bl31_ep_info->args.arg1);
2224f6ad66aSAchin Gupta }
223