1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <platform_def.h> 32 33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 34OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 35ENTRY(bl1_entrypoint) 36 37MEMORY { 38 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE 39 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE 40} 41 42SECTIONS 43{ 44 . = BL1_RO_BASE; 45 ASSERT(. == ALIGN(4096), 46 "BL1_RO_BASE address is not aligned on a page boundary.") 47 48 ro . : { 49 __RO_START__ = .; 50 *bl1_entrypoint.o(.text*) 51 *(.text*) 52 *(.rodata*) 53 54 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 55 . = ALIGN(8); 56 __PARSER_LIB_DESCS_START__ = .; 57 KEEP(*(.img_parser_lib_descs)) 58 __PARSER_LIB_DESCS_END__ = .; 59 60 /* 61 * Ensure 8-byte alignment for cpu_ops so that its fields are also 62 * aligned. Also ensure cpu_ops inclusion. 63 */ 64 . = ALIGN(8); 65 __CPU_OPS_START__ = .; 66 KEEP(*(cpu_ops)) 67 __CPU_OPS_END__ = .; 68 69 *(.vectors) 70 __RO_END__ = .; 71 } >ROM 72 73 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 74 "cpu_ops not defined for this platform.") 75 76 /* 77 * The .data section gets copied from ROM to RAM at runtime. 78 * Its LMA must be 16-byte aligned. 79 * Its VMA must be page-aligned as it marks the first read/write page. 80 */ 81 . = BL1_RW_BASE; 82 ASSERT(. == ALIGN(4096), 83 "BL1_RW_BASE address is not aligned on a page boundary.") 84 .data . : ALIGN(16) { 85 __DATA_RAM_START__ = .; 86 *(.data*) 87 __DATA_RAM_END__ = .; 88 } >RAM AT>ROM 89 90 stacks . (NOLOAD) : { 91 __STACKS_START__ = .; 92 *(tzfw_normal_stacks) 93 __STACKS_END__ = .; 94 } >RAM 95 96 /* 97 * The .bss section gets initialised to 0 at runtime. 98 * Its base address must be 16-byte aligned. 99 */ 100 .bss : ALIGN(16) { 101 __BSS_START__ = .; 102 *(.bss*) 103 *(COMMON) 104 __BSS_END__ = .; 105 } >RAM 106 107 /* 108 * The xlat_table section is for full, aligned page tables (4K). 109 * Removing them from .bss avoids forcing 4K alignment on 110 * the .bss section and eliminates the unecessary zero init 111 */ 112 xlat_table (NOLOAD) : { 113 *(xlat_table) 114 } >RAM 115 116#if USE_COHERENT_MEM 117 /* 118 * The base address of the coherent memory section must be page-aligned (4K) 119 * to guarantee that the coherent data are stored on their own pages and 120 * are not mixed with normal data. This is required to set up the correct 121 * memory attributes for the coherent data page tables. 122 */ 123 coherent_ram (NOLOAD) : ALIGN(4096) { 124 __COHERENT_RAM_START__ = .; 125 *(tzfw_coherent_mem) 126 __COHERENT_RAM_END_UNALIGNED__ = .; 127 /* 128 * Memory page(s) mapped to this section will be marked 129 * as device memory. No other unexpected data must creep in. 130 * Ensure the rest of the current memory page is unused. 131 */ 132 . = NEXT(4096); 133 __COHERENT_RAM_END__ = .; 134 } >RAM 135#endif 136 137 __BL1_RAM_START__ = ADDR(.data); 138 __BL1_RAM_END__ = .; 139 140 __DATA_ROM_START__ = LOADADDR(.data); 141 __DATA_SIZE__ = SIZEOF(.data); 142 /* 143 * The .data section is the last PROGBITS section so its end marks the end 144 * of the read-only part of BL1's binary. 145 */ 146 ASSERT(__DATA_ROM_START__ + __DATA_SIZE__ <= BL1_RO_LIMIT, 147 "BL1's RO section has exceeded its limit.") 148 149 __BSS_SIZE__ = SIZEOF(.bss); 150 151#if USE_COHERENT_MEM 152 __COHERENT_RAM_UNALIGNED_SIZE__ = 153 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 154#endif 155 156 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") 157} 158