1/* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/* 8 * The .data section gets copied from ROM to RAM at runtime. Its LMA should be 9 * 16-byte aligned to allow efficient copying of 16-bytes aligned regions in it. 10 * Its VMA must be page-aligned as it marks the first read/write page. 11 */ 12#define DATA_ALIGN 16 13 14#include <common/bl_common.ld.h> 15#include <lib/xlat_tables/xlat_tables_defs.h> 16 17OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 18OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 19ENTRY(bl1_entrypoint) 20 21MEMORY { 22 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE 23 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE 24} 25 26SECTIONS { 27 ROM_REGION_START = ORIGIN(ROM); 28 ROM_REGION_LENGTH = LENGTH(ROM); 29 RAM_REGION_START = ORIGIN(RAM); 30 RAM_REGION_LENGTH = LENGTH(RAM); 31 32 . = BL1_RO_BASE; 33 34 ASSERT(. == ALIGN(PAGE_SIZE), 35 "BL1_RO_BASE address is not aligned on a page boundary.") 36 37#if SEPARATE_CODE_AND_RODATA 38 .text . : { 39 __TEXT_START__ = .; 40 41 *bl1_entrypoint.o(.text*) 42 *(SORT_BY_ALIGNMENT(.text*)) 43 *(.vectors) 44 45 . = ALIGN(PAGE_SIZE); 46 47 __TEXT_END__ = .; 48 } >ROM 49 50 /* .ARM.extab and .ARM.exidx are only added because Clang needs them */ 51 .ARM.extab . : { 52 *(.ARM.extab* .gnu.linkonce.armextab.*) 53 } >ROM 54 55 .ARM.exidx . : { 56 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 57 } >ROM 58 59 .rodata . : { 60 __RODATA_START__ = .; 61 62 *(SORT_BY_ALIGNMENT(.rodata*)) 63 64 RODATA_COMMON 65 66 /* 67 * No need to pad out the .rodata section to a page boundary. Next is 68 * the .data section, which can mapped in ROM with the same memory 69 * attributes as the .rodata section. 70 * 71 * Pad out to 16 bytes though as .data section needs to be 16-byte 72 * aligned and lld does not align the LMA to the alignment specified 73 * on the .data section. 74 */ 75 __RODATA_END__ = .; 76 77 . = ALIGN(16); 78 } >ROM 79#else /* SEPARATE_CODE_AND_RODATA */ 80 .ro . : { 81 __RO_START__ = .; 82 83 *bl1_entrypoint.o(.text*) 84 *(SORT_BY_ALIGNMENT(.text*)) 85 *(SORT_BY_ALIGNMENT(.rodata*)) 86 87 RODATA_COMMON 88 89 *(.vectors) 90 91 __RO_END__ = .; 92 93 /* 94 * Pad out to 16 bytes as the .data section needs to be 16-byte aligned 95 * and lld does not align the LMA to the alignment specified on the 96 * .data section. 97 */ 98 . = ALIGN(16); 99 } >ROM 100#endif /* SEPARATE_CODE_AND_RODATA */ 101 102 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 103 "cpu_ops not defined for this platform.") 104 105 ROM_REGION_END = .; 106 . = BL1_RW_BASE; 107 108 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE), 109 "BL1_RW_BASE address is not aligned on a page boundary.") 110 111 DATA_SECTION >RAM AT>ROM 112 113 __DATA_RAM_START__ = __DATA_START__; 114 __DATA_RAM_END__ = __DATA_END__; 115 116 STACK_SECTION >RAM 117 BSS_SECTION >RAM 118 XLAT_TABLE_SECTION >RAM 119 120#if USE_COHERENT_MEM 121 /* 122 * The base address of the coherent memory section must be page-aligned to 123 * guarantee that the coherent data are stored on their own pages and are 124 * not mixed with normal data. This is required to set up the correct memory 125 * attributes for the coherent data page tables. 126 */ 127 .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 128 __COHERENT_RAM_START__ = .; 129 *(.tzfw_coherent_mem) 130 __COHERENT_RAM_END_UNALIGNED__ = .; 131 132 /* 133 * Memory page(s) mapped to this section will be marked as device 134 * memory. No other unexpected data must creep in. Ensure the rest of 135 * the current memory page is unused. 136 */ 137 . = ALIGN(PAGE_SIZE); 138 139 __COHERENT_RAM_END__ = .; 140 } >RAM 141#endif /* USE_COHERENT_MEM */ 142 143 __BL1_RAM_START__ = ADDR(.data); 144 __BL1_RAM_END__ = .; 145 146 __DATA_ROM_START__ = LOADADDR(.data); 147 __DATA_SIZE__ = SIZEOF(.data); 148 149 /* 150 * The .data section is the last PROGBITS section so its end marks the end 151 * of BL1's actual content in Trusted ROM. 152 */ 153 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 154 155 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT, 156 "BL1's ROM content has exceeded its limit.") 157 158 __BSS_SIZE__ = SIZEOF(.bss); 159 160#if USE_COHERENT_MEM 161 __COHERENT_RAM_UNALIGNED_SIZE__ = 162 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 163#endif /* USE_COHERENT_MEM */ 164 165 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") 166 RAM_REGION_END = .; 167} 168