1/* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <common/bl_common.ld.h> 10#include <lib/xlat_tables/xlat_tables_defs.h> 11 12OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 13OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 14ENTRY(bl1_entrypoint) 15 16MEMORY { 17 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE 18 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE 19} 20 21SECTIONS 22{ 23 . = BL1_RO_BASE; 24 ASSERT(. == ALIGN(PAGE_SIZE), 25 "BL1_RO_BASE address is not aligned on a page boundary.") 26 27#if SEPARATE_CODE_AND_RODATA 28 .text . : { 29 __TEXT_START__ = .; 30 *bl1_entrypoint.o(.text*) 31 *(SORT_BY_ALIGNMENT(.text*)) 32 *(.vectors) 33 . = ALIGN(PAGE_SIZE); 34 __TEXT_END__ = .; 35 } >ROM 36 37 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 38 .ARM.extab . : { 39 *(.ARM.extab* .gnu.linkonce.armextab.*) 40 } >ROM 41 42 .ARM.exidx . : { 43 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 44 } >ROM 45 46 .rodata . : { 47 __RODATA_START__ = .; 48 *(SORT_BY_ALIGNMENT(.rodata*)) 49 50 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 51 . = ALIGN(8); 52 __PARSER_LIB_DESCS_START__ = .; 53 KEEP(*(.img_parser_lib_descs)) 54 __PARSER_LIB_DESCS_END__ = .; 55 56 /* 57 * Ensure 8-byte alignment for cpu_ops so that its fields are also 58 * aligned. Also ensure cpu_ops inclusion. 59 */ 60 . = ALIGN(8); 61 __CPU_OPS_START__ = .; 62 KEEP(*(cpu_ops)) 63 __CPU_OPS_END__ = .; 64 65 /* 66 * No need to pad out the .rodata section to a page boundary. Next is 67 * the .data section, which can mapped in ROM with the same memory 68 * attributes as the .rodata section. 69 * 70 * Pad out to 16 bytes though as .data section needs to be 16 byte 71 * aligned and lld does not align the LMA to the aligment specified 72 * on the .data section. 73 */ 74 __RODATA_END__ = .; 75 . = ALIGN(16); 76 } >ROM 77#else 78 ro . : { 79 __RO_START__ = .; 80 *bl1_entrypoint.o(.text*) 81 *(SORT_BY_ALIGNMENT(.text*)) 82 *(SORT_BY_ALIGNMENT(.rodata*)) 83 84 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 85 . = ALIGN(8); 86 __PARSER_LIB_DESCS_START__ = .; 87 KEEP(*(.img_parser_lib_descs)) 88 __PARSER_LIB_DESCS_END__ = .; 89 90 /* 91 * Ensure 8-byte alignment for cpu_ops so that its fields are also 92 * aligned. Also ensure cpu_ops inclusion. 93 */ 94 . = ALIGN(8); 95 __CPU_OPS_START__ = .; 96 KEEP(*(cpu_ops)) 97 __CPU_OPS_END__ = .; 98 99 *(.vectors) 100 __RO_END__ = .; 101 102 /* 103 * Pad out to 16 bytes as .data section needs to be 16 byte aligned and 104 * lld does not align the LMA to the aligment specified on the .data 105 * section. 106 */ 107 . = ALIGN(16); 108 } >ROM 109#endif 110 111 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 112 "cpu_ops not defined for this platform.") 113 114 . = BL1_RW_BASE; 115 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE), 116 "BL1_RW_BASE address is not aligned on a page boundary.") 117 118 /* 119 * The .data section gets copied from ROM to RAM at runtime. 120 * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes 121 * aligned regions in it. 122 * Its VMA must be page-aligned as it marks the first read/write page. 123 * 124 * It must be placed at a lower address than the stacks if the stack 125 * protector is enabled. Alternatively, the .data.stack_protector_canary 126 * section can be placed independently of the main .data section. 127 */ 128 .data . : ALIGN(16) { 129 __DATA_RAM_START__ = .; 130 *(SORT_BY_ALIGNMENT(.data*)) 131 __DATA_RAM_END__ = .; 132 } >RAM AT>ROM 133 134 stacks . (NOLOAD) : { 135 __STACKS_START__ = .; 136 *(tzfw_normal_stacks) 137 __STACKS_END__ = .; 138 } >RAM 139 140 /* 141 * The .bss section gets initialised to 0 at runtime. 142 * Its base address should be 16-byte aligned for better performance of the 143 * zero-initialization code. 144 */ 145 .bss : ALIGN(16) { 146 __BSS_START__ = .; 147 *(SORT_BY_ALIGNMENT(.bss*)) 148 *(COMMON) 149 __BSS_END__ = .; 150 } >RAM 151 152 XLAT_TABLE_SECTION >RAM 153 154#if USE_COHERENT_MEM 155 /* 156 * The base address of the coherent memory section must be page-aligned (4K) 157 * to guarantee that the coherent data are stored on their own pages and 158 * are not mixed with normal data. This is required to set up the correct 159 * memory attributes for the coherent data page tables. 160 */ 161 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 162 __COHERENT_RAM_START__ = .; 163 *(tzfw_coherent_mem) 164 __COHERENT_RAM_END_UNALIGNED__ = .; 165 /* 166 * Memory page(s) mapped to this section will be marked 167 * as device memory. No other unexpected data must creep in. 168 * Ensure the rest of the current memory page is unused. 169 */ 170 . = ALIGN(PAGE_SIZE); 171 __COHERENT_RAM_END__ = .; 172 } >RAM 173#endif 174 175 __BL1_RAM_START__ = ADDR(.data); 176 __BL1_RAM_END__ = .; 177 178 __DATA_ROM_START__ = LOADADDR(.data); 179 __DATA_SIZE__ = SIZEOF(.data); 180 181 /* 182 * The .data section is the last PROGBITS section so its end marks the end 183 * of BL1's actual content in Trusted ROM. 184 */ 185 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 186 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT, 187 "BL1's ROM content has exceeded its limit.") 188 189 __BSS_SIZE__ = SIZEOF(.bss); 190 191#if USE_COHERENT_MEM 192 __COHERENT_RAM_UNALIGNED_SIZE__ = 193 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 194#endif 195 196 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") 197} 198