1/* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <platform_def.h> 32 33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 34OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 35ENTRY(bl1_entrypoint) 36 37MEMORY { 38 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE 39 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE 40} 41 42SECTIONS 43{ 44 . = BL1_RO_BASE; 45 ASSERT(. == ALIGN(4096), 46 "BL1_RO_BASE address is not aligned on a page boundary.") 47 48#if SEPARATE_CODE_AND_RODATA 49 .text . : { 50 __TEXT_START__ = .; 51 *bl1_entrypoint.o(.text*) 52 *(.text*) 53 *(.vectors) 54 . = NEXT(4096); 55 __TEXT_END__ = .; 56 } >ROM 57 58 .rodata . : { 59 __RODATA_START__ = .; 60 *(.rodata*) 61 62 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 63 . = ALIGN(8); 64 __PARSER_LIB_DESCS_START__ = .; 65 KEEP(*(.img_parser_lib_descs)) 66 __PARSER_LIB_DESCS_END__ = .; 67 68 /* 69 * Ensure 8-byte alignment for cpu_ops so that its fields are also 70 * aligned. Also ensure cpu_ops inclusion. 71 */ 72 . = ALIGN(8); 73 __CPU_OPS_START__ = .; 74 KEEP(*(cpu_ops)) 75 __CPU_OPS_END__ = .; 76 77 /* 78 * No need to pad out the .rodata section to a page boundary. Next is 79 * the .data section, which can mapped in ROM with the same memory 80 * attributes as the .rodata section. 81 */ 82 __RODATA_END__ = .; 83 } >ROM 84#else 85 ro . : { 86 __RO_START__ = .; 87 *bl1_entrypoint.o(.text*) 88 *(.text*) 89 *(.rodata*) 90 91 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 92 . = ALIGN(8); 93 __PARSER_LIB_DESCS_START__ = .; 94 KEEP(*(.img_parser_lib_descs)) 95 __PARSER_LIB_DESCS_END__ = .; 96 97 /* 98 * Ensure 8-byte alignment for cpu_ops so that its fields are also 99 * aligned. Also ensure cpu_ops inclusion. 100 */ 101 . = ALIGN(8); 102 __CPU_OPS_START__ = .; 103 KEEP(*(cpu_ops)) 104 __CPU_OPS_END__ = .; 105 106 *(.vectors) 107 __RO_END__ = .; 108 } >ROM 109#endif 110 111 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 112 "cpu_ops not defined for this platform.") 113 114 /* 115 * The .data section gets copied from ROM to RAM at runtime. 116 * Its LMA must be 16-byte aligned. 117 * Its VMA must be page-aligned as it marks the first read/write page. 118 */ 119 . = BL1_RW_BASE; 120 ASSERT(. == ALIGN(4096), 121 "BL1_RW_BASE address is not aligned on a page boundary.") 122 .data . : ALIGN(16) { 123 __DATA_RAM_START__ = .; 124 *(.data*) 125 __DATA_RAM_END__ = .; 126 } >RAM AT>ROM 127 128 stacks . (NOLOAD) : { 129 __STACKS_START__ = .; 130 *(tzfw_normal_stacks) 131 __STACKS_END__ = .; 132 } >RAM 133 134 /* 135 * The .bss section gets initialised to 0 at runtime. 136 * Its base address should be 16-byte aligned for better performance of the 137 * zero-initialization code. 138 */ 139 .bss : ALIGN(16) { 140 __BSS_START__ = .; 141 *(.bss*) 142 *(COMMON) 143 __BSS_END__ = .; 144 } >RAM 145 146 /* 147 * The xlat_table section is for full, aligned page tables (4K). 148 * Removing them from .bss avoids forcing 4K alignment on 149 * the .bss section and eliminates the unecessary zero init 150 */ 151 xlat_table (NOLOAD) : { 152 *(xlat_table) 153 } >RAM 154 155#if USE_COHERENT_MEM 156 /* 157 * The base address of the coherent memory section must be page-aligned (4K) 158 * to guarantee that the coherent data are stored on their own pages and 159 * are not mixed with normal data. This is required to set up the correct 160 * memory attributes for the coherent data page tables. 161 */ 162 coherent_ram (NOLOAD) : ALIGN(4096) { 163 __COHERENT_RAM_START__ = .; 164 *(tzfw_coherent_mem) 165 __COHERENT_RAM_END_UNALIGNED__ = .; 166 /* 167 * Memory page(s) mapped to this section will be marked 168 * as device memory. No other unexpected data must creep in. 169 * Ensure the rest of the current memory page is unused. 170 */ 171 . = NEXT(4096); 172 __COHERENT_RAM_END__ = .; 173 } >RAM 174#endif 175 176 __BL1_RAM_START__ = ADDR(.data); 177 __BL1_RAM_END__ = .; 178 179 __DATA_ROM_START__ = LOADADDR(.data); 180 __DATA_SIZE__ = SIZEOF(.data); 181 182 /* 183 * The .data section is the last PROGBITS section so its end marks the end 184 * of BL1's actual content in Trusted ROM. 185 */ 186 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 187 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT, 188 "BL1's ROM content has exceeded its limit.") 189 190 __BSS_SIZE__ = SIZEOF(.bss); 191 192#if USE_COHERENT_MEM 193 __COHERENT_RAM_UNALIGNED_SIZE__ = 194 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 195#endif 196 197 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") 198} 199