1/* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <lib/xlat_tables/xlat_tables_defs.h> 10 11OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 12OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 13ENTRY(bl1_entrypoint) 14 15MEMORY { 16 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE 17 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE 18} 19 20SECTIONS 21{ 22 . = BL1_RO_BASE; 23 ASSERT(. == ALIGN(PAGE_SIZE), 24 "BL1_RO_BASE address is not aligned on a page boundary.") 25 26#if SEPARATE_CODE_AND_RODATA 27 .text . : { 28 __TEXT_START__ = .; 29 *bl1_entrypoint.o(.text*) 30 *(SORT_BY_ALIGNMENT(.text*)) 31 *(.vectors) 32 . = ALIGN(PAGE_SIZE); 33 __TEXT_END__ = .; 34 } >ROM 35 36 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 37 .ARM.extab . : { 38 *(.ARM.extab* .gnu.linkonce.armextab.*) 39 } >ROM 40 41 .ARM.exidx . : { 42 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 43 } >ROM 44 45 .rodata . : { 46 __RODATA_START__ = .; 47 *(SORT_BY_ALIGNMENT(.rodata*)) 48 49 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 50 . = ALIGN(8); 51 __PARSER_LIB_DESCS_START__ = .; 52 KEEP(*(.img_parser_lib_descs)) 53 __PARSER_LIB_DESCS_END__ = .; 54 55 /* 56 * Ensure 8-byte alignment for cpu_ops so that its fields are also 57 * aligned. Also ensure cpu_ops inclusion. 58 */ 59 . = ALIGN(8); 60 __CPU_OPS_START__ = .; 61 KEEP(*(cpu_ops)) 62 __CPU_OPS_END__ = .; 63 64 /* 65 * No need to pad out the .rodata section to a page boundary. Next is 66 * the .data section, which can mapped in ROM with the same memory 67 * attributes as the .rodata section. 68 * 69 * Pad out to 16 bytes though as .data section needs to be 16 byte 70 * aligned and lld does not align the LMA to the aligment specified 71 * on the .data section. 72 */ 73 __RODATA_END__ = .; 74 . = ALIGN(16); 75 } >ROM 76#else 77 ro . : { 78 __RO_START__ = .; 79 *bl1_entrypoint.o(.text*) 80 *(SORT_BY_ALIGNMENT(.text*)) 81 *(SORT_BY_ALIGNMENT(.rodata*)) 82 83 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 84 . = ALIGN(8); 85 __PARSER_LIB_DESCS_START__ = .; 86 KEEP(*(.img_parser_lib_descs)) 87 __PARSER_LIB_DESCS_END__ = .; 88 89 /* 90 * Ensure 8-byte alignment for cpu_ops so that its fields are also 91 * aligned. Also ensure cpu_ops inclusion. 92 */ 93 . = ALIGN(8); 94 __CPU_OPS_START__ = .; 95 KEEP(*(cpu_ops)) 96 __CPU_OPS_END__ = .; 97 98 *(.vectors) 99 __RO_END__ = .; 100 101 /* 102 * Pad out to 16 bytes as .data section needs to be 16 byte aligned and 103 * lld does not align the LMA to the aligment specified on the .data 104 * section. 105 */ 106 . = ALIGN(16); 107 } >ROM 108#endif 109 110 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 111 "cpu_ops not defined for this platform.") 112 113 . = BL1_RW_BASE; 114 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE), 115 "BL1_RW_BASE address is not aligned on a page boundary.") 116 117 /* 118 * The .data section gets copied from ROM to RAM at runtime. 119 * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes 120 * aligned regions in it. 121 * Its VMA must be page-aligned as it marks the first read/write page. 122 * 123 * It must be placed at a lower address than the stacks if the stack 124 * protector is enabled. Alternatively, the .data.stack_protector_canary 125 * section can be placed independently of the main .data section. 126 */ 127 .data . : ALIGN(16) { 128 __DATA_RAM_START__ = .; 129 *(SORT_BY_ALIGNMENT(.data*)) 130 __DATA_RAM_END__ = .; 131 } >RAM AT>ROM 132 133 stacks . (NOLOAD) : { 134 __STACKS_START__ = .; 135 *(tzfw_normal_stacks) 136 __STACKS_END__ = .; 137 } >RAM 138 139 /* 140 * The .bss section gets initialised to 0 at runtime. 141 * Its base address should be 16-byte aligned for better performance of the 142 * zero-initialization code. 143 */ 144 .bss : ALIGN(16) { 145 __BSS_START__ = .; 146 *(SORT_BY_ALIGNMENT(.bss*)) 147 *(COMMON) 148 __BSS_END__ = .; 149 } >RAM 150 151 /* 152 * The xlat_table section is for full, aligned page tables (4K). 153 * Removing them from .bss avoids forcing 4K alignment on 154 * the .bss section. The tables are initialized to zero by the translation 155 * tables library. 156 */ 157 xlat_table (NOLOAD) : { 158 *(xlat_table) 159 } >RAM 160 161#if USE_COHERENT_MEM 162 /* 163 * The base address of the coherent memory section must be page-aligned (4K) 164 * to guarantee that the coherent data are stored on their own pages and 165 * are not mixed with normal data. This is required to set up the correct 166 * memory attributes for the coherent data page tables. 167 */ 168 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 169 __COHERENT_RAM_START__ = .; 170 *(tzfw_coherent_mem) 171 __COHERENT_RAM_END_UNALIGNED__ = .; 172 /* 173 * Memory page(s) mapped to this section will be marked 174 * as device memory. No other unexpected data must creep in. 175 * Ensure the rest of the current memory page is unused. 176 */ 177 . = ALIGN(PAGE_SIZE); 178 __COHERENT_RAM_END__ = .; 179 } >RAM 180#endif 181 182 __BL1_RAM_START__ = ADDR(.data); 183 __BL1_RAM_END__ = .; 184 185 __DATA_ROM_START__ = LOADADDR(.data); 186 __DATA_SIZE__ = SIZEOF(.data); 187 188 /* 189 * The .data section is the last PROGBITS section so its end marks the end 190 * of BL1's actual content in Trusted ROM. 191 */ 192 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 193 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT, 194 "BL1's ROM content has exceeded its limit.") 195 196 __BSS_SIZE__ = SIZEOF(.bss); 197 198#if USE_COHERENT_MEM 199 __COHERENT_RAM_UNALIGNED_SIZE__ = 200 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 201#endif 202 203 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") 204} 205