1/* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/* 8 * The .data section gets copied from ROM to RAM at runtime. Its LMA should be 9 * 16-byte aligned to allow efficient copying of 16-bytes aligned regions in it. 10 * Its VMA must be page-aligned as it marks the first read/write page. 11 */ 12#define DATA_ALIGN 16 13 14#include <common/bl_common.ld.h> 15#include <lib/xlat_tables/xlat_tables_defs.h> 16 17OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 18OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 19ENTRY(bl1_entrypoint) 20 21MEMORY { 22 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE 23 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE 24} 25 26SECTIONS { 27 ROM_REGION_START = ORIGIN(ROM); 28 ROM_REGION_LENGTH = LENGTH(ROM); 29 RAM_REGION_START = ORIGIN(RAM); 30 RAM_REGION_LENGTH = LENGTH(RAM); 31 32 . = BL1_RO_BASE; 33 34 ASSERT(. == ALIGN(PAGE_SIZE), 35 "BL1_RO_BASE address is not aligned on a page boundary.") 36 37#if SEPARATE_CODE_AND_RODATA 38 .text . : { 39 ASSERT(. == ALIGN(PAGE_SIZE), 40 ".text address is not aligned on a page boundary."); 41 42 __TEXT_START__ = .; 43 44 *bl1_entrypoint.o(.text*) 45 *(SORT_BY_ALIGNMENT(.text*)) 46 *(.vectors) 47 __TEXT_END_UNALIGNED__ = .; 48 49 . = ALIGN(PAGE_SIZE); 50 51 __TEXT_END__ = .; 52 } >ROM 53 54 /* .ARM.extab and .ARM.exidx are only added because Clang needs them */ 55 .ARM.extab . : { 56 *(.ARM.extab* .gnu.linkonce.armextab.*) 57 } >ROM 58 59 .ARM.exidx . : { 60 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 61 } >ROM 62 63 .rodata . : { 64 __RODATA_START__ = .; 65 66 *(SORT_BY_ALIGNMENT(.rodata*)) 67 68 RODATA_COMMON 69 70 /* 71 * No need to pad out the .rodata section to a page boundary. Next is 72 * the .data section, which can mapped in ROM with the same memory 73 * attributes as the .rodata section. 74 * 75 * Pad out to 16 bytes though as .data section needs to be 16-byte 76 * aligned and lld does not align the LMA to the alignment specified 77 * on the .data section. 78 */ 79 __RODATA_END_UNALIGNED__ = .; 80 __RODATA_END__ = .; 81 82 . = ALIGN(16); 83 } >ROM 84#else /* SEPARATE_CODE_AND_RODATA */ 85 .ro . : { 86 ASSERT(. == ALIGN(PAGE_SIZE), 87 ".ro address is not aligned on a page boundary."); 88 89 __RO_START__ = .; 90 91 *bl1_entrypoint.o(.text*) 92 *(SORT_BY_ALIGNMENT(.text*)) 93 *(SORT_BY_ALIGNMENT(.rodata*)) 94 95 RODATA_COMMON 96 97 *(.vectors) 98 99 __RO_END__ = .; 100 101 /* 102 * Pad out to 16 bytes as the .data section needs to be 16-byte aligned 103 * and lld does not align the LMA to the alignment specified on the 104 * .data section. 105 */ 106 . = ALIGN(16); 107 } >ROM 108#endif /* SEPARATE_CODE_AND_RODATA */ 109 110 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 111 "cpu_ops not defined for this platform.") 112 113 ROM_REGION_END = .; 114 . = BL1_RW_BASE; 115 116 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE), 117 "BL1_RW_BASE address is not aligned on a page boundary.") 118 119 DATA_SECTION >RAM AT>ROM 120 121 __DATA_RAM_START__ = __DATA_START__; 122 __DATA_RAM_END__ = __DATA_END__; 123 124 STACK_SECTION >RAM 125 BSS_SECTION >RAM 126 XLAT_TABLE_SECTION >RAM 127 128#if USE_COHERENT_MEM 129 /* 130 * The base address of the coherent memory section must be page-aligned to 131 * guarantee that the coherent data are stored on their own pages and are 132 * not mixed with normal data. This is required to set up the correct memory 133 * attributes for the coherent data page tables. 134 */ 135 .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 136 __COHERENT_RAM_START__ = .; 137 *(.tzfw_coherent_mem) 138 __COHERENT_RAM_END_UNALIGNED__ = .; 139 140 /* 141 * Memory page(s) mapped to this section will be marked as device 142 * memory. No other unexpected data must creep in. Ensure the rest of 143 * the current memory page is unused. 144 */ 145 . = ALIGN(PAGE_SIZE); 146 147 __COHERENT_RAM_END__ = .; 148 } >RAM 149#endif /* USE_COHERENT_MEM */ 150 151 __BL1_RAM_START__ = ADDR(.data); 152 __BL1_RAM_END__ = .; 153 154 __DATA_ROM_START__ = LOADADDR(.data); 155 __DATA_SIZE__ = SIZEOF(.data); 156 157 /* 158 * The .data section is the last PROGBITS section so its end marks the end 159 * of BL1's actual content in Trusted ROM. 160 */ 161 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 162 163 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT, 164 "BL1's ROM content has exceeded its limit.") 165 166 __BSS_SIZE__ = SIZEOF(.bss); 167 168#if USE_COHERENT_MEM 169 __COHERENT_RAM_UNALIGNED_SIZE__ = 170 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 171#endif /* USE_COHERENT_MEM */ 172 173 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") 174 RAM_REGION_END = .; 175} 176