1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <platform.h> 32 33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 34OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 35 36MEMORY { 37 ROM (rx): ORIGIN = TZROM_BASE, LENGTH = TZROM_SIZE 38 RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE 39} 40 41SECTIONS 42{ 43 ro : { 44 __RO_START__ = .; 45 *bl1_entrypoint.o(.text) 46 *(.text) 47 *(.rodata*) 48 *(.vectors) 49 __RO_END__ = .; 50 } >ROM 51 52 /* 53 * The .data section gets copied from ROM to RAM at runtime. 54 * Its LMA and VMA must be 16-byte aligned. 55 */ 56 . = NEXT(16); /* Align LMA */ 57 .data : ALIGN(16) { /* Align VMA */ 58 __DATA_RAM_START__ = .; 59 *(.data) 60 __DATA_RAM_END__ = .; 61 } >RAM AT>ROM 62 63 stacks (NOLOAD) : { 64 __STACKS_START__ = .; 65 *(tzfw_normal_stacks) 66 __STACKS_END__ = .; 67 } >RAM 68 69 /* 70 * The .bss section gets initialised to 0 at runtime. 71 * Its base address must be 16-byte aligned. 72 */ 73 .bss : ALIGN(16) { 74 __BSS_START__ = .; 75 *(.bss) 76 *(COMMON) 77 __BSS_END__ = .; 78 } >RAM 79 80 /* 81 * The xlat_table section is for full, aligned page tables (4K). 82 * Removing them from .bss avoids forcing 4K alignment on 83 * the .bss section and eliminates the unecessary zero init 84 */ 85 xlat_table (NOLOAD) : { 86 *(xlat_table) 87 } >RAM 88 89 /* 90 * The base address of the coherent memory section must be page-aligned (4K) 91 * to guarantee that the coherent data are stored on their own pages and 92 * are not mixed with normal data. This is required to set up the correct 93 * memory attributes for the coherent data page tables. 94 */ 95 coherent_ram (NOLOAD) : ALIGN(4096) { 96 __COHERENT_RAM_START__ = .; 97 *(tzfw_coherent_mem) 98 __COHERENT_RAM_END_UNALIGNED__ = .; 99 /* 100 * Memory page(s) mapped to this section will be marked 101 * as device memory. No other unexpected data must creep in. 102 * Ensure the rest of the current memory page is unused. 103 */ 104 . = NEXT(4096); 105 __COHERENT_RAM_END__ = .; 106 } >RAM 107 108 __BL1_RAM_START__ = ADDR(.data); 109 __BL1_RAM_END__ = .; 110 111 __DATA_ROM_START__ = LOADADDR(.data); 112 __DATA_SIZE__ = SIZEOF(.data); 113 114 __BSS_SIZE__ = SIZEOF(.bss); 115 116 __COHERENT_RAM_UNALIGNED_SIZE__ = 117 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 118 119 ASSERT(. <= BL31_BASE, "BL1 image overlaps BL31 image.") 120} 121