1/* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8#include <xlat_tables_defs.h> 9 10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 11OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 12ENTRY(bl1_entrypoint) 13 14MEMORY { 15 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE 16 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE 17} 18 19SECTIONS 20{ 21 . = BL1_RO_BASE; 22 ASSERT(. == ALIGN(PAGE_SIZE), 23 "BL1_RO_BASE address is not aligned on a page boundary.") 24 25#if SEPARATE_CODE_AND_RODATA 26 .text . : { 27 __TEXT_START__ = .; 28 *bl1_entrypoint.o(.text*) 29 *(.text*) 30 *(.vectors) 31 . = ALIGN(PAGE_SIZE); 32 __TEXT_END__ = .; 33 } >ROM 34 35 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 36 .ARM.extab . : { 37 *(.ARM.extab* .gnu.linkonce.armextab.*) 38 } >ROM 39 40 .ARM.exidx . : { 41 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 42 } >ROM 43 44 .rodata . : { 45 __RODATA_START__ = .; 46 *(.rodata*) 47 48 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 49 . = ALIGN(8); 50 __PARSER_LIB_DESCS_START__ = .; 51 KEEP(*(.img_parser_lib_descs)) 52 __PARSER_LIB_DESCS_END__ = .; 53 54 /* 55 * Ensure 8-byte alignment for cpu_ops so that its fields are also 56 * aligned. Also ensure cpu_ops inclusion. 57 */ 58 . = ALIGN(8); 59 __CPU_OPS_START__ = .; 60 KEEP(*(cpu_ops)) 61 __CPU_OPS_END__ = .; 62 63 /* 64 * No need to pad out the .rodata section to a page boundary. Next is 65 * the .data section, which can mapped in ROM with the same memory 66 * attributes as the .rodata section. 67 */ 68 __RODATA_END__ = .; 69 } >ROM 70#else 71 ro . : { 72 __RO_START__ = .; 73 *bl1_entrypoint.o(.text*) 74 *(.text*) 75 *(.rodata*) 76 77 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 78 . = ALIGN(8); 79 __PARSER_LIB_DESCS_START__ = .; 80 KEEP(*(.img_parser_lib_descs)) 81 __PARSER_LIB_DESCS_END__ = .; 82 83 /* 84 * Ensure 8-byte alignment for cpu_ops so that its fields are also 85 * aligned. Also ensure cpu_ops inclusion. 86 */ 87 . = ALIGN(8); 88 __CPU_OPS_START__ = .; 89 KEEP(*(cpu_ops)) 90 __CPU_OPS_END__ = .; 91 92 *(.vectors) 93 __RO_END__ = .; 94 } >ROM 95#endif 96 97 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 98 "cpu_ops not defined for this platform.") 99 100 . = BL1_RW_BASE; 101 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE), 102 "BL1_RW_BASE address is not aligned on a page boundary.") 103 104 /* 105 * The .data section gets copied from ROM to RAM at runtime. 106 * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes 107 * aligned regions in it. 108 * Its VMA must be page-aligned as it marks the first read/write page. 109 * 110 * It must be placed at a lower address than the stacks if the stack 111 * protector is enabled. Alternatively, the .data.stack_protector_canary 112 * section can be placed independently of the main .data section. 113 */ 114 .data . : ALIGN(16) { 115 __DATA_RAM_START__ = .; 116 *(.data*) 117 __DATA_RAM_END__ = .; 118 } >RAM AT>ROM 119 120 stacks . (NOLOAD) : { 121 __STACKS_START__ = .; 122 *(tzfw_normal_stacks) 123 __STACKS_END__ = .; 124 } >RAM 125 126 /* 127 * The .bss section gets initialised to 0 at runtime. 128 * Its base address should be 16-byte aligned for better performance of the 129 * zero-initialization code. 130 */ 131 .bss : ALIGN(16) { 132 __BSS_START__ = .; 133 *(.bss*) 134 *(COMMON) 135 __BSS_END__ = .; 136 } >RAM 137 138 /* 139 * The xlat_table section is for full, aligned page tables (4K). 140 * Removing them from .bss avoids forcing 4K alignment on 141 * the .bss section. The tables are initialized to zero by the translation 142 * tables library. 143 */ 144 xlat_table (NOLOAD) : { 145 *(xlat_table) 146 } >RAM 147 148#if USE_COHERENT_MEM 149 /* 150 * The base address of the coherent memory section must be page-aligned (4K) 151 * to guarantee that the coherent data are stored on their own pages and 152 * are not mixed with normal data. This is required to set up the correct 153 * memory attributes for the coherent data page tables. 154 */ 155 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 156 __COHERENT_RAM_START__ = .; 157 *(tzfw_coherent_mem) 158 __COHERENT_RAM_END_UNALIGNED__ = .; 159 /* 160 * Memory page(s) mapped to this section will be marked 161 * as device memory. No other unexpected data must creep in. 162 * Ensure the rest of the current memory page is unused. 163 */ 164 . = ALIGN(PAGE_SIZE); 165 __COHERENT_RAM_END__ = .; 166 } >RAM 167#endif 168 169 __BL1_RAM_START__ = ADDR(.data); 170 __BL1_RAM_END__ = .; 171 172 __DATA_ROM_START__ = LOADADDR(.data); 173 __DATA_SIZE__ = SIZEOF(.data); 174 175 /* 176 * The .data section is the last PROGBITS section so its end marks the end 177 * of BL1's actual content in Trusted ROM. 178 */ 179 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 180 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT, 181 "BL1's ROM content has exceeded its limit.") 182 183 __BSS_SIZE__ = SIZEOF(.bss); 184 185#if USE_COHERENT_MEM 186 __COHERENT_RAM_UNALIGNED_SIZE__ = 187 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 188#endif 189 190 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") 191} 192