xref: /rk3399_ARM-atf/bl1/bl1.ld.S (revision 9f98aa1a7e33dd55851fd4feec0de9b40b6d9f10)
14f6ad66aSAchin Gupta/*
2e83b0cadSDan Handley * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
34f6ad66aSAchin Gupta *
44f6ad66aSAchin Gupta * Redistribution and use in source and binary forms, with or without
54f6ad66aSAchin Gupta * modification, are permitted provided that the following conditions are met:
64f6ad66aSAchin Gupta *
74f6ad66aSAchin Gupta * Redistributions of source code must retain the above copyright notice, this
84f6ad66aSAchin Gupta * list of conditions and the following disclaimer.
94f6ad66aSAchin Gupta *
104f6ad66aSAchin Gupta * Redistributions in binary form must reproduce the above copyright notice,
114f6ad66aSAchin Gupta * this list of conditions and the following disclaimer in the documentation
124f6ad66aSAchin Gupta * and/or other materials provided with the distribution.
134f6ad66aSAchin Gupta *
144f6ad66aSAchin Gupta * Neither the name of ARM nor the names of its contributors may be used
154f6ad66aSAchin Gupta * to endorse or promote products derived from this software without specific
164f6ad66aSAchin Gupta * prior written permission.
174f6ad66aSAchin Gupta *
184f6ad66aSAchin Gupta * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
194f6ad66aSAchin Gupta * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
204f6ad66aSAchin Gupta * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
214f6ad66aSAchin Gupta * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
224f6ad66aSAchin Gupta * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
234f6ad66aSAchin Gupta * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
244f6ad66aSAchin Gupta * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
254f6ad66aSAchin Gupta * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
264f6ad66aSAchin Gupta * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
274f6ad66aSAchin Gupta * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
284f6ad66aSAchin Gupta * POSSIBILITY OF SUCH DAMAGE.
294f6ad66aSAchin Gupta */
304f6ad66aSAchin Gupta
314f6ad66aSAchin Gupta#include <platform.h>
324f6ad66aSAchin Gupta
334f6ad66aSAchin GuptaOUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
344f6ad66aSAchin GuptaOUTPUT_ARCH(PLATFORM_LINKER_ARCH)
35*9f98aa1aSJeenu ViswambharanENTRY(bl1_entrypoint)
364f6ad66aSAchin Gupta
374f6ad66aSAchin GuptaMEMORY {
384f6ad66aSAchin Gupta    ROM (rx): ORIGIN = TZROM_BASE, LENGTH = TZROM_SIZE
394f6ad66aSAchin Gupta    RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
404f6ad66aSAchin Gupta}
414f6ad66aSAchin Gupta
424f6ad66aSAchin GuptaSECTIONS
434f6ad66aSAchin Gupta{
448d69a03fSSandrine Bailleux    ro : {
458d69a03fSSandrine Bailleux        __RO_START__ = .;
468d69a03fSSandrine Bailleux        *bl1_entrypoint.o(.text)
474f6ad66aSAchin Gupta        *(.text)
488d69a03fSSandrine Bailleux        *(.rodata*)
49b739f22aSAchin Gupta        *(.vectors)
508d69a03fSSandrine Bailleux        __RO_END__ = .;
514f6ad66aSAchin Gupta    } >ROM
524f6ad66aSAchin Gupta
538d69a03fSSandrine Bailleux    /*
548d69a03fSSandrine Bailleux     * The .data section gets copied from ROM to RAM at runtime.
558d69a03fSSandrine Bailleux     * Its LMA and VMA must be 16-byte aligned.
568d69a03fSSandrine Bailleux     */
578d69a03fSSandrine Bailleux    . = NEXT(16);        /* Align LMA */
588d69a03fSSandrine Bailleux    .data : ALIGN(16) {  /* Align VMA */
594f6ad66aSAchin Gupta        __DATA_RAM_START__ = .;
604f6ad66aSAchin Gupta        *(.data)
618d69a03fSSandrine Bailleux        __DATA_RAM_END__ = .;
624f6ad66aSAchin Gupta    } >RAM AT>ROM
634f6ad66aSAchin Gupta
648d69a03fSSandrine Bailleux    stacks (NOLOAD) : {
658d69a03fSSandrine Bailleux        __STACKS_START__ = .;
664f6ad66aSAchin Gupta        *(tzfw_normal_stacks)
678d69a03fSSandrine Bailleux        __STACKS_END__ = .;
684f6ad66aSAchin Gupta    } >RAM
694f6ad66aSAchin Gupta
708d69a03fSSandrine Bailleux    /*
718d69a03fSSandrine Bailleux     * The .bss section gets initialised to 0 at runtime.
728d69a03fSSandrine Bailleux     * Its base address must be 16-byte aligned.
738d69a03fSSandrine Bailleux     */
748d69a03fSSandrine Bailleux    .bss : ALIGN(16) {
758d69a03fSSandrine Bailleux        __BSS_START__ = .;
768d69a03fSSandrine Bailleux        *(.bss)
778d69a03fSSandrine Bailleux        *(COMMON)
788d69a03fSSandrine Bailleux        __BSS_END__ = .;
798d69a03fSSandrine Bailleux    } >RAM
804f6ad66aSAchin Gupta
818d69a03fSSandrine Bailleux    /*
82a0cd989dSAchin Gupta     * The xlat_table section is for full, aligned page tables (4K).
8374cbb839SJeenu Viswambharan     * Removing them from .bss avoids forcing 4K alignment on
8474cbb839SJeenu Viswambharan     * the .bss section and eliminates the unecessary zero init
8574cbb839SJeenu Viswambharan     */
8674cbb839SJeenu Viswambharan    xlat_table (NOLOAD) : {
8774cbb839SJeenu Viswambharan        *(xlat_table)
8874cbb839SJeenu Viswambharan    } >RAM
8974cbb839SJeenu Viswambharan
9074cbb839SJeenu Viswambharan    /*
918d69a03fSSandrine Bailleux     * The base address of the coherent memory section must be page-aligned (4K)
928d69a03fSSandrine Bailleux     * to guarantee that the coherent data are stored on their own pages and
938d69a03fSSandrine Bailleux     * are not mixed with normal data.  This is required to set up the correct
948d69a03fSSandrine Bailleux     * memory attributes for the coherent data page tables.
958d69a03fSSandrine Bailleux     */
968d69a03fSSandrine Bailleux    coherent_ram (NOLOAD) : ALIGN(4096) {
978d69a03fSSandrine Bailleux        __COHERENT_RAM_START__ = .;
988d69a03fSSandrine Bailleux        *(tzfw_coherent_mem)
998d69a03fSSandrine Bailleux        __COHERENT_RAM_END_UNALIGNED__ = .;
1008d69a03fSSandrine Bailleux        /*
1018d69a03fSSandrine Bailleux         * Memory page(s) mapped to this section will be marked
1028d69a03fSSandrine Bailleux         * as device memory.  No other unexpected data must creep in.
1038d69a03fSSandrine Bailleux         * Ensure the rest of the current memory page is unused.
1048d69a03fSSandrine Bailleux         */
1058d69a03fSSandrine Bailleux        . = NEXT(4096);
1068d69a03fSSandrine Bailleux        __COHERENT_RAM_END__ = .;
1078d69a03fSSandrine Bailleux    } >RAM
1084f6ad66aSAchin Gupta
1098d69a03fSSandrine Bailleux    __BL1_RAM_START__ = ADDR(.data);
1108d69a03fSSandrine Bailleux    __BL1_RAM_END__ = .;
1114f6ad66aSAchin Gupta
1128d69a03fSSandrine Bailleux    __DATA_ROM_START__ = LOADADDR(.data);
1138d69a03fSSandrine Bailleux    __DATA_SIZE__ = SIZEOF(.data);
1148d69a03fSSandrine Bailleux
1158d69a03fSSandrine Bailleux    __BSS_SIZE__ = SIZEOF(.bss);
1168d69a03fSSandrine Bailleux
1178d69a03fSSandrine Bailleux    __COHERENT_RAM_UNALIGNED_SIZE__ =
1188d69a03fSSandrine Bailleux        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
1198d69a03fSSandrine Bailleux
120e4d084eaSAchin Gupta    ASSERT(. <= BL31_BASE, "BL1 image overlaps BL31 image.")
1214f6ad66aSAchin Gupta}
122