1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <bl_common.h> 34#include <runtime_svc.h> 35 36 .globl bl1_exceptions 37 38 .section .vectors, "ax"; .align 11 39 40 /* ----------------------------------------------------- 41 * Very simple stackless exception handlers used by BL1. 42 * ----------------------------------------------------- 43 */ 44 .align 7 45bl1_exceptions: 46 /* ----------------------------------------------------- 47 * Current EL with SP0 : 0x0 - 0x180 48 * ----------------------------------------------------- 49 */ 50SynchronousExceptionSP0: 51 mov x0, #SYNC_EXCEPTION_SP_EL0 52 bl plat_report_exception 53 b SynchronousExceptionSP0 54 check_vector_size SynchronousExceptionSP0 55 56 .align 7 57IrqSP0: 58 mov x0, #IRQ_SP_EL0 59 bl plat_report_exception 60 b IrqSP0 61 check_vector_size IrqSP0 62 63 .align 7 64FiqSP0: 65 mov x0, #FIQ_SP_EL0 66 bl plat_report_exception 67 b FiqSP0 68 check_vector_size FiqSP0 69 70 .align 7 71SErrorSP0: 72 mov x0, #SERROR_SP_EL0 73 bl plat_report_exception 74 b SErrorSP0 75 check_vector_size SErrorSP0 76 77 /* ----------------------------------------------------- 78 * Current EL with SPx: 0x200 - 0x380 79 * ----------------------------------------------------- 80 */ 81 .align 7 82SynchronousExceptionSPx: 83 mov x0, #SYNC_EXCEPTION_SP_ELX 84 bl plat_report_exception 85 b SynchronousExceptionSPx 86 check_vector_size SynchronousExceptionSPx 87 88 .align 7 89IrqSPx: 90 mov x0, #IRQ_SP_ELX 91 bl plat_report_exception 92 b IrqSPx 93 check_vector_size IrqSPx 94 95 .align 7 96FiqSPx: 97 mov x0, #FIQ_SP_ELX 98 bl plat_report_exception 99 b FiqSPx 100 check_vector_size FiqSPx 101 102 .align 7 103SErrorSPx: 104 mov x0, #SERROR_SP_ELX 105 bl plat_report_exception 106 b SErrorSPx 107 check_vector_size SErrorSPx 108 109 /* ----------------------------------------------------- 110 * Lower EL using AArch64 : 0x400 - 0x580 111 * ----------------------------------------------------- 112 */ 113 .align 7 114SynchronousExceptionA64: 115 /* ------------------------------------------------ 116 * Only a single SMC exception from BL2 to ask 117 * BL1 to pass EL3 control to BL31 is expected 118 * here. 119 * It expects X0 with RUN_IMAGE SMC function id 120 * X1 with address of a entry_point_info_t structure 121 * describing the BL3-1 entrypoint 122 * ------------------------------------------------ 123 */ 124 mov x19, x0 125 mov x20, x1 126 127 mrs x0, esr_el3 128 ubfx x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH 129 cmp x1, #EC_AARCH64_SMC 130 b.ne panic 131 132 mov x0, #RUN_IMAGE 133 cmp x19, x0 134 b.ne panic 135 136 mov x0, x20 137 bl display_boot_progress 138 139 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 140 msr elr_el3, x0 141 msr spsr_el3, x1 142 ubfx x0, x1, #MODE_EL_SHIFT, #2 143 cmp x0, #MODE_EL3 144 b.ne panic 145 146 bl disable_mmu_icache_el3 147 tlbi alle3 148 149 ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 150 ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 151 ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 152 ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 153 eret 154panic: 155 mov x0, #SYNC_EXCEPTION_AARCH64 156 bl plat_report_exception 157 158 wfi 159 b panic 160 check_vector_size SynchronousExceptionA64 161 162 .align 7 163IrqA64: 164 mov x0, #IRQ_AARCH64 165 bl plat_report_exception 166 b IrqA64 167 check_vector_size IrqA64 168 169 .align 7 170FiqA64: 171 mov x0, #FIQ_AARCH64 172 bl plat_report_exception 173 b FiqA64 174 check_vector_size FiqA64 175 176 .align 7 177SErrorA64: 178 mov x0, #SERROR_AARCH64 179 bl plat_report_exception 180 b SErrorA64 181 check_vector_size SErrorA64 182 183 /* ----------------------------------------------------- 184 * Lower EL using AArch32 : 0x0 - 0x180 185 * ----------------------------------------------------- 186 */ 187 .align 7 188SynchronousExceptionA32: 189 mov x0, #SYNC_EXCEPTION_AARCH32 190 bl plat_report_exception 191 b SynchronousExceptionA32 192 check_vector_size SynchronousExceptionA32 193 194 .align 7 195IrqA32: 196 mov x0, #IRQ_AARCH32 197 bl plat_report_exception 198 b IrqA32 199 check_vector_size IrqA32 200 201 .align 7 202FiqA32: 203 mov x0, #FIQ_AARCH32 204 bl plat_report_exception 205 b FiqA32 206 check_vector_size FiqA32 207 208 .align 7 209SErrorA32: 210 mov x0, #SERROR_AARCH32 211 bl plat_report_exception 212 b SErrorA32 213 check_vector_size SErrorA32 214