1/* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <bl_common.h> 34 35 .globl bl1_exceptions 36 37 .section .vectors, "ax"; .align 11 38 39 /* ----------------------------------------------------- 40 * Very simple stackless exception handlers used by BL1. 41 * ----------------------------------------------------- 42 */ 43 .align 7 44bl1_exceptions: 45 /* ----------------------------------------------------- 46 * Current EL with SP0 : 0x0 - 0x200 47 * ----------------------------------------------------- 48 */ 49SynchronousExceptionSP0: 50 mov x0, #SYNC_EXCEPTION_SP_EL0 51 bl plat_report_exception 52 b SynchronousExceptionSP0 53 check_vector_size SynchronousExceptionSP0 54 55 .align 7 56IrqSP0: 57 mov x0, #IRQ_SP_EL0 58 bl plat_report_exception 59 b IrqSP0 60 check_vector_size IrqSP0 61 62 .align 7 63FiqSP0: 64 mov x0, #FIQ_SP_EL0 65 bl plat_report_exception 66 b FiqSP0 67 check_vector_size FiqSP0 68 69 .align 7 70SErrorSP0: 71 mov x0, #SERROR_SP_EL0 72 bl plat_report_exception 73 b SErrorSP0 74 check_vector_size SErrorSP0 75 76 /* ----------------------------------------------------- 77 * Current EL with SPx: 0x200 - 0x400 78 * ----------------------------------------------------- 79 */ 80 .align 7 81SynchronousExceptionSPx: 82 mov x0, #SYNC_EXCEPTION_SP_ELX 83 bl plat_report_exception 84 b SynchronousExceptionSPx 85 check_vector_size SynchronousExceptionSPx 86 87 .align 7 88IrqSPx: 89 mov x0, #IRQ_SP_ELX 90 bl plat_report_exception 91 b IrqSPx 92 check_vector_size IrqSPx 93 94 .align 7 95FiqSPx: 96 mov x0, #FIQ_SP_ELX 97 bl plat_report_exception 98 b FiqSPx 99 check_vector_size FiqSPx 100 101 .align 7 102SErrorSPx: 103 mov x0, #SERROR_SP_ELX 104 bl plat_report_exception 105 b SErrorSPx 106 check_vector_size SErrorSPx 107 108 /* ----------------------------------------------------- 109 * Lower EL using AArch64 : 0x400 - 0x600 110 * ----------------------------------------------------- 111 */ 112 .align 7 113SynchronousExceptionA64: 114 /* Enable the SError interrupt */ 115 msr daifclr, #DAIF_ABT_BIT 116 117 /* Expect only SMC exceptions */ 118 mrs x19, esr_el3 119 ubfx x20, x19, #ESR_EC_SHIFT, #ESR_EC_LENGTH 120 cmp x20, #EC_AARCH64_SMC 121 b.ne unexpected_sync_exception 122 123 b smc_handler64 124 check_vector_size SynchronousExceptionA64 125 126 .align 7 127IrqA64: 128 mov x0, #IRQ_AARCH64 129 bl plat_report_exception 130 b IrqA64 131 check_vector_size IrqA64 132 133 .align 7 134FiqA64: 135 mov x0, #FIQ_AARCH64 136 bl plat_report_exception 137 b FiqA64 138 check_vector_size FiqA64 139 140 .align 7 141SErrorA64: 142 mov x0, #SERROR_AARCH64 143 bl plat_report_exception 144 b SErrorA64 145 check_vector_size SErrorA64 146 147 /* ----------------------------------------------------- 148 * Lower EL using AArch32 : 0x600 - 0x800 149 * ----------------------------------------------------- 150 */ 151 .align 7 152SynchronousExceptionA32: 153 mov x0, #SYNC_EXCEPTION_AARCH32 154 bl plat_report_exception 155 b SynchronousExceptionA32 156 check_vector_size SynchronousExceptionA32 157 158 .align 7 159IrqA32: 160 mov x0, #IRQ_AARCH32 161 bl plat_report_exception 162 b IrqA32 163 check_vector_size IrqA32 164 165 .align 7 166FiqA32: 167 mov x0, #FIQ_AARCH32 168 bl plat_report_exception 169 b FiqA32 170 check_vector_size FiqA32 171 172 .align 7 173SErrorA32: 174 mov x0, #SERROR_AARCH32 175 bl plat_report_exception 176 b SErrorA32 177 check_vector_size SErrorA32 178 179 180func smc_handler64 181 /* --------------------------------------------------------------------- 182 * Only a single SMC exception from BL2 to ask BL1 to pass EL3 control 183 * to BL31 is expected here. It expects: 184 * - X0 with RUN_IMAGE SMC function ID; 185 * - X1 with the address of a entry_point_info_t structure describing 186 * the BL31 entrypoint. 187 * --------------------------------------------------------------------- 188 */ 189 mov x19, x0 190 mov x20, x1 191 192 mov x0, #RUN_IMAGE 193 cmp x19, x0 194 b.ne unexpected_sync_exception 195 196 mov x0, x20 197 bl bl1_print_bl31_ep_info 198 199 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 200 msr elr_el3, x0 201 msr spsr_el3, x1 202 ubfx x0, x1, #MODE_EL_SHIFT, #2 203 cmp x0, #MODE_EL3 204 b.ne unexpected_sync_exception 205 206 bl disable_mmu_icache_el3 207 tlbi alle3 208 209#if SPIN_ON_BL1_EXIT 210 bl print_debug_loop_message 211debug_loop: 212 b debug_loop 213#endif 214 215 mov x0, x20 216 bl bl1_plat_prepare_exit 217 218 ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 219 ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 220 ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 221 ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 222 eret 223endfunc smc_handler64 224 225unexpected_sync_exception: 226 mov x0, #SYNC_EXCEPTION_AARCH64 227 bl plat_report_exception 228 wfi 229 b unexpected_sync_exception 230