1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <bl_common.h> 34#include <runtime_svc.h> 35 36 .globl bl1_exceptions 37 38 .section .vectors, "ax"; .align 11 39 40 /* ----------------------------------------------------- 41 * Very simple stackless exception handlers used by BL1. 42 * ----------------------------------------------------- 43 */ 44 .align 7 45bl1_exceptions: 46 /* ----------------------------------------------------- 47 * Current EL with SP0 : 0x0 - 0x180 48 * ----------------------------------------------------- 49 */ 50SynchronousExceptionSP0: 51 mov x0, #SYNC_EXCEPTION_SP_EL0 52 bl plat_report_exception 53 b SynchronousExceptionSP0 54 check_vector_size SynchronousExceptionSP0 55 56 .align 7 57IrqSP0: 58 mov x0, #IRQ_SP_EL0 59 bl plat_report_exception 60 b IrqSP0 61 check_vector_size IrqSP0 62 63 .align 7 64FiqSP0: 65 mov x0, #FIQ_SP_EL0 66 bl plat_report_exception 67 b FiqSP0 68 check_vector_size FiqSP0 69 70 .align 7 71SErrorSP0: 72 mov x0, #SERROR_SP_EL0 73 bl plat_report_exception 74 b SErrorSP0 75 check_vector_size SErrorSP0 76 77 /* ----------------------------------------------------- 78 * Current EL with SPx: 0x200 - 0x380 79 * ----------------------------------------------------- 80 */ 81 .align 7 82SynchronousExceptionSPx: 83 mov x0, #SYNC_EXCEPTION_SP_ELX 84 bl plat_report_exception 85 b SynchronousExceptionSPx 86 check_vector_size SynchronousExceptionSPx 87 88 .align 7 89IrqSPx: 90 mov x0, #IRQ_SP_ELX 91 bl plat_report_exception 92 b IrqSPx 93 check_vector_size IrqSPx 94 95 .align 7 96FiqSPx: 97 mov x0, #FIQ_SP_ELX 98 bl plat_report_exception 99 b FiqSPx 100 check_vector_size FiqSPx 101 102 .align 7 103SErrorSPx: 104 mov x0, #SERROR_SP_ELX 105 bl plat_report_exception 106 b SErrorSPx 107 check_vector_size SErrorSPx 108 109 /* ----------------------------------------------------- 110 * Lower EL using AArch64 : 0x400 - 0x580 111 * ----------------------------------------------------- 112 */ 113 .align 7 114SynchronousExceptionA64: 115 /* --------------------------------------------- 116 * Only a single SMC exception from BL2 to ask 117 * BL1 to pass EL3 control to BL31 is expected 118 * here. 119 * --------------------------------------------- 120 */ 121 b process_exception 122 check_vector_size SynchronousExceptionA64 123 124 .align 7 125IrqA64: 126 mov x0, #IRQ_AARCH64 127 bl plat_report_exception 128 b IrqA64 129 check_vector_size IrqA64 130 131 .align 7 132FiqA64: 133 mov x0, #FIQ_AARCH64 134 bl plat_report_exception 135 b FiqA64 136 check_vector_size FiqA64 137 138 .align 7 139SErrorA64: 140 mov x0, #SERROR_AARCH64 141 bl plat_report_exception 142 b SErrorA64 143 check_vector_size SErrorA64 144 145 /* ----------------------------------------------------- 146 * Lower EL using AArch32 : 0x0 - 0x180 147 * ----------------------------------------------------- 148 */ 149 .align 7 150SynchronousExceptionA32: 151 mov x0, #SYNC_EXCEPTION_AARCH32 152 bl plat_report_exception 153 b SynchronousExceptionA32 154 check_vector_size SynchronousExceptionA32 155 156 .align 7 157IrqA32: 158 mov x0, #IRQ_AARCH32 159 bl plat_report_exception 160 b IrqA32 161 check_vector_size IrqA32 162 163 .align 7 164FiqA32: 165 mov x0, #FIQ_AARCH32 166 bl plat_report_exception 167 b FiqA32 168 check_vector_size FiqA32 169 170 .align 7 171SErrorA32: 172 mov x0, #SERROR_AARCH32 173 bl plat_report_exception 174 b SErrorA32 175 check_vector_size SErrorA32 176 177 .align 7 178 179func process_exception 180 sub sp, sp, #0x40 181 stp x0, x1, [sp, #0x0] 182 stp x2, x3, [sp, #0x10] 183 stp x4, x5, [sp, #0x20] 184 stp x6, x7, [sp, #0x30] 185 186 mov x19, x0 187 mov x20, x1 188 mov x21, x2 189 mov x0, #SYNC_EXCEPTION_AARCH64 190 bl plat_report_exception 191 192 bl read_esr_el3 193 ubfx x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH 194 cmp x1, #EC_AARCH64_SMC 195 b.ne panic 196 mov x1, #RUN_IMAGE 197 cmp x19, x1 198 b.ne panic 199 mov x0, x20 200 mov x1, x21 201 mov x2, x3 202 mov x3, x4 203 bl display_boot_progress 204 mov x0, x20 205 bl write_elr 206 mov x0, x21 207 bl write_spsr 208 ubfx x0, x21, #MODE_EL_SHIFT, #2 209 cmp x0, #MODE_EL3 210 b.ne skip_mmu_teardown 211 212 /* --------------------------------------------- 213 * If BL31 is to be executed in EL3 as well 214 * then turn off the MMU so that it can perform 215 * its own setup. TODO: Assuming flat mapped 216 * translations here. Also all should go into a 217 * separate MMU teardown function 218 * --------------------------------------------- 219 */ 220 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) 221 bl read_sctlr_el3 222 bic x0, x0, x1 223 bl write_sctlr_el3 224 mov x0, #DCCISW 225 bl dcsw_op_all 226 bl tlbialle3 227skip_mmu_teardown: 228 ldp x6, x7, [sp, #0x30] 229 ldp x4, x5, [sp, #0x20] 230 ldp x2, x3, [sp, #0x10] 231 ldp x0, x1, [sp, #0x0] 232 add sp, sp, #0x40 233 eret 234 235panic: 236 wfi 237 b panic 238