1/* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <bl_common.h> 34#include <context.h> 35 36 .globl bl1_exceptions 37 38 .section .vectors, "ax"; .align 11 39 40 /* ----------------------------------------------------- 41 * Very simple stackless exception handlers used by BL1. 42 * ----------------------------------------------------- 43 */ 44 .align 7 45bl1_exceptions: 46 /* ----------------------------------------------------- 47 * Current EL with SP0 : 0x0 - 0x200 48 * ----------------------------------------------------- 49 */ 50SynchronousExceptionSP0: 51 mov x0, #SYNC_EXCEPTION_SP_EL0 52 bl plat_report_exception 53 b SynchronousExceptionSP0 54 check_vector_size SynchronousExceptionSP0 55 56 .align 7 57IrqSP0: 58 mov x0, #IRQ_SP_EL0 59 bl plat_report_exception 60 b IrqSP0 61 check_vector_size IrqSP0 62 63 .align 7 64FiqSP0: 65 mov x0, #FIQ_SP_EL0 66 bl plat_report_exception 67 b FiqSP0 68 check_vector_size FiqSP0 69 70 .align 7 71SErrorSP0: 72 mov x0, #SERROR_SP_EL0 73 bl plat_report_exception 74 b SErrorSP0 75 check_vector_size SErrorSP0 76 77 /* ----------------------------------------------------- 78 * Current EL with SPx: 0x200 - 0x400 79 * ----------------------------------------------------- 80 */ 81 .align 7 82SynchronousExceptionSPx: 83 mov x0, #SYNC_EXCEPTION_SP_ELX 84 bl plat_report_exception 85 b SynchronousExceptionSPx 86 check_vector_size SynchronousExceptionSPx 87 88 .align 7 89IrqSPx: 90 mov x0, #IRQ_SP_ELX 91 bl plat_report_exception 92 b IrqSPx 93 check_vector_size IrqSPx 94 95 .align 7 96FiqSPx: 97 mov x0, #FIQ_SP_ELX 98 bl plat_report_exception 99 b FiqSPx 100 check_vector_size FiqSPx 101 102 .align 7 103SErrorSPx: 104 mov x0, #SERROR_SP_ELX 105 bl plat_report_exception 106 b SErrorSPx 107 check_vector_size SErrorSPx 108 109 /* ----------------------------------------------------- 110 * Lower EL using AArch64 : 0x400 - 0x600 111 * ----------------------------------------------------- 112 */ 113 .align 7 114SynchronousExceptionA64: 115 /* Enable the SError interrupt */ 116 msr daifclr, #DAIF_ABT_BIT 117 118 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 119 120 /* Expect only SMC exceptions */ 121 mrs x30, esr_el3 122 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 123 cmp x30, #EC_AARCH64_SMC 124 b.ne unexpected_sync_exception 125 126 b smc_handler64 127 check_vector_size SynchronousExceptionA64 128 129 .align 7 130IrqA64: 131 mov x0, #IRQ_AARCH64 132 bl plat_report_exception 133 b IrqA64 134 check_vector_size IrqA64 135 136 .align 7 137FiqA64: 138 mov x0, #FIQ_AARCH64 139 bl plat_report_exception 140 b FiqA64 141 check_vector_size FiqA64 142 143 .align 7 144SErrorA64: 145 mov x0, #SERROR_AARCH64 146 bl plat_report_exception 147 b SErrorA64 148 check_vector_size SErrorA64 149 150 /* ----------------------------------------------------- 151 * Lower EL using AArch32 : 0x600 - 0x800 152 * ----------------------------------------------------- 153 */ 154 .align 7 155SynchronousExceptionA32: 156 mov x0, #SYNC_EXCEPTION_AARCH32 157 bl plat_report_exception 158 b SynchronousExceptionA32 159 check_vector_size SynchronousExceptionA32 160 161 .align 7 162IrqA32: 163 mov x0, #IRQ_AARCH32 164 bl plat_report_exception 165 b IrqA32 166 check_vector_size IrqA32 167 168 .align 7 169FiqA32: 170 mov x0, #FIQ_AARCH32 171 bl plat_report_exception 172 b FiqA32 173 check_vector_size FiqA32 174 175 .align 7 176SErrorA32: 177 mov x0, #SERROR_AARCH32 178 bl plat_report_exception 179 b SErrorA32 180 check_vector_size SErrorA32 181 182 183func smc_handler64 184 /* ---------------------------------------------- 185 * Switch back to SP_EL0 for the C runtime stack. 186 * ---------------------------------------------- 187 */ 188 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 189 msr spsel, #0 190 mov sp, x30 191 192 /* --------------------------------------------------------------------- 193 * Only a single SMC exception from BL2 to ask BL1 to pass EL3 control 194 * to BL31 is expected here. It expects: 195 * - X0 with RUN_IMAGE SMC function ID; 196 * - X1 with the address of a entry_point_info_t structure describing 197 * the BL31 entrypoint. 198 * --------------------------------------------------------------------- 199 */ 200 mov x19, x0 201 mov x20, x1 202 203 mov x0, #RUN_IMAGE 204 cmp x19, x0 205 b.ne unexpected_sync_exception 206 207 mov x0, x20 208 bl bl1_print_bl31_ep_info 209 210 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 211 msr elr_el3, x0 212 msr spsr_el3, x1 213 ubfx x0, x1, #MODE_EL_SHIFT, #2 214 cmp x0, #MODE_EL3 215 b.ne unexpected_sync_exception 216 217 bl disable_mmu_icache_el3 218 tlbi alle3 219 220#if SPIN_ON_BL1_EXIT 221 bl print_debug_loop_message 222debug_loop: 223 b debug_loop 224#endif 225 226 mov x0, x20 227 bl bl1_plat_prepare_exit 228 229 ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 230 ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 231 ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 232 ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 233 eret 234endfunc smc_handler64 235 236unexpected_sync_exception: 237 mov x0, #SYNC_EXCEPTION_AARCH64 238 bl plat_report_exception 239 wfi 240 b unexpected_sync_exception 241