1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <bl_common.h> 34#include <runtime_svc.h> 35 36 .globl bl1_exceptions 37 38 .section .vectors, "ax"; .align 11 39 40 /* ----------------------------------------------------- 41 * Very simple stackless exception handlers used by BL1. 42 * ----------------------------------------------------- 43 */ 44 .align 7 45bl1_exceptions: 46 /* ----------------------------------------------------- 47 * Current EL with SP0 : 0x0 - 0x200 48 * ----------------------------------------------------- 49 */ 50SynchronousExceptionSP0: 51 mov x0, #SYNC_EXCEPTION_SP_EL0 52 bl plat_report_exception 53 b SynchronousExceptionSP0 54 check_vector_size SynchronousExceptionSP0 55 56 .align 7 57IrqSP0: 58 mov x0, #IRQ_SP_EL0 59 bl plat_report_exception 60 b IrqSP0 61 check_vector_size IrqSP0 62 63 .align 7 64FiqSP0: 65 mov x0, #FIQ_SP_EL0 66 bl plat_report_exception 67 b FiqSP0 68 check_vector_size FiqSP0 69 70 .align 7 71SErrorSP0: 72 mov x0, #SERROR_SP_EL0 73 bl plat_report_exception 74 b SErrorSP0 75 check_vector_size SErrorSP0 76 77 /* ----------------------------------------------------- 78 * Current EL with SPx: 0x200 - 0x400 79 * ----------------------------------------------------- 80 */ 81 .align 7 82SynchronousExceptionSPx: 83 mov x0, #SYNC_EXCEPTION_SP_ELX 84 bl plat_report_exception 85 b SynchronousExceptionSPx 86 check_vector_size SynchronousExceptionSPx 87 88 .align 7 89IrqSPx: 90 mov x0, #IRQ_SP_ELX 91 bl plat_report_exception 92 b IrqSPx 93 check_vector_size IrqSPx 94 95 .align 7 96FiqSPx: 97 mov x0, #FIQ_SP_ELX 98 bl plat_report_exception 99 b FiqSPx 100 check_vector_size FiqSPx 101 102 .align 7 103SErrorSPx: 104 mov x0, #SERROR_SP_ELX 105 bl plat_report_exception 106 b SErrorSPx 107 check_vector_size SErrorSPx 108 109 /* ----------------------------------------------------- 110 * Lower EL using AArch64 : 0x400 - 0x600 111 * ----------------------------------------------------- 112 */ 113 .align 7 114SynchronousExceptionA64: 115 /* Enable the SError interrupt */ 116 msr daifclr, #DAIF_ABT_BIT 117 118 /* Expect only SMC exceptions */ 119 mrs x19, esr_el3 120 ubfx x20, x19, #ESR_EC_SHIFT, #ESR_EC_LENGTH 121 cmp x20, #EC_AARCH64_SMC 122 b.ne unexpected_sync_exception 123 124 b smc_handler64 125 check_vector_size SynchronousExceptionA64 126 127 .align 7 128IrqA64: 129 mov x0, #IRQ_AARCH64 130 bl plat_report_exception 131 b IrqA64 132 check_vector_size IrqA64 133 134 .align 7 135FiqA64: 136 mov x0, #FIQ_AARCH64 137 bl plat_report_exception 138 b FiqA64 139 check_vector_size FiqA64 140 141 .align 7 142SErrorA64: 143 mov x0, #SERROR_AARCH64 144 bl plat_report_exception 145 b SErrorA64 146 check_vector_size SErrorA64 147 148 /* ----------------------------------------------------- 149 * Lower EL using AArch32 : 0x600 - 0x800 150 * ----------------------------------------------------- 151 */ 152 .align 7 153SynchronousExceptionA32: 154 mov x0, #SYNC_EXCEPTION_AARCH32 155 bl plat_report_exception 156 b SynchronousExceptionA32 157 check_vector_size SynchronousExceptionA32 158 159 .align 7 160IrqA32: 161 mov x0, #IRQ_AARCH32 162 bl plat_report_exception 163 b IrqA32 164 check_vector_size IrqA32 165 166 .align 7 167FiqA32: 168 mov x0, #FIQ_AARCH32 169 bl plat_report_exception 170 b FiqA32 171 check_vector_size FiqA32 172 173 .align 7 174SErrorA32: 175 mov x0, #SERROR_AARCH32 176 bl plat_report_exception 177 b SErrorA32 178 check_vector_size SErrorA32 179 180 181func smc_handler64 182 /* --------------------------------------------------------------------- 183 * Only a single SMC exception from BL2 to ask BL1 to pass EL3 control 184 * to BL31 is expected here. It expects: 185 * - X0 with RUN_IMAGE SMC function ID; 186 * - X1 with the address of a entry_point_info_t structure describing 187 * the BL31 entrypoint. 188 * --------------------------------------------------------------------- 189 */ 190 mov x19, x0 191 mov x20, x1 192 193 mov x0, #RUN_IMAGE 194 cmp x19, x0 195 b.ne unexpected_sync_exception 196 197 mov x0, x20 198 bl bl1_print_bl31_ep_info 199 200 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 201 msr elr_el3, x0 202 msr spsr_el3, x1 203 ubfx x0, x1, #MODE_EL_SHIFT, #2 204 cmp x0, #MODE_EL3 205 b.ne unexpected_sync_exception 206 207 bl disable_mmu_icache_el3 208 tlbi alle3 209 210#if SPIN_ON_BL1_EXIT 211 bl print_debug_loop_message 212debug_loop: 213 b debug_loop 214#endif 215 216 mov x0, x20 217 bl bl1_plat_prepare_exit 218 219 ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 220 ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 221 ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 222 ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 223 eret 224endfunc smc_handler64 225 226unexpected_sync_exception: 227 mov x0, #SYNC_EXCEPTION_AARCH64 228 bl plat_report_exception 229 wfi 230 b unexpected_sync_exception 231