1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <bl_common.h> 34#include <bl1.h> 35#include <context.h> 36 37/* ----------------------------------------------------------------------------- 38 * Very simple stackless exception handlers used by BL1. 39 * ----------------------------------------------------------------------------- 40 */ 41 .globl bl1_exceptions 42 43vector_base bl1_exceptions 44 45 /* ----------------------------------------------------- 46 * Current EL with SP0 : 0x0 - 0x200 47 * ----------------------------------------------------- 48 */ 49vector_entry SynchronousExceptionSP0 50 mov x0, #SYNC_EXCEPTION_SP_EL0 51 bl plat_report_exception 52 b SynchronousExceptionSP0 53 check_vector_size SynchronousExceptionSP0 54 55vector_entry IrqSP0 56 mov x0, #IRQ_SP_EL0 57 bl plat_report_exception 58 b IrqSP0 59 check_vector_size IrqSP0 60 61vector_entry FiqSP0 62 mov x0, #FIQ_SP_EL0 63 bl plat_report_exception 64 b FiqSP0 65 check_vector_size FiqSP0 66 67vector_entry SErrorSP0 68 mov x0, #SERROR_SP_EL0 69 bl plat_report_exception 70 b SErrorSP0 71 check_vector_size SErrorSP0 72 73 /* ----------------------------------------------------- 74 * Current EL with SPx: 0x200 - 0x400 75 * ----------------------------------------------------- 76 */ 77vector_entry SynchronousExceptionSPx 78 mov x0, #SYNC_EXCEPTION_SP_ELX 79 bl plat_report_exception 80 b SynchronousExceptionSPx 81 check_vector_size SynchronousExceptionSPx 82 83vector_entry IrqSPx 84 mov x0, #IRQ_SP_ELX 85 bl plat_report_exception 86 b IrqSPx 87 check_vector_size IrqSPx 88 89vector_entry FiqSPx 90 mov x0, #FIQ_SP_ELX 91 bl plat_report_exception 92 b FiqSPx 93 check_vector_size FiqSPx 94 95vector_entry SErrorSPx 96 mov x0, #SERROR_SP_ELX 97 bl plat_report_exception 98 b SErrorSPx 99 check_vector_size SErrorSPx 100 101 /* ----------------------------------------------------- 102 * Lower EL using AArch64 : 0x400 - 0x600 103 * ----------------------------------------------------- 104 */ 105vector_entry SynchronousExceptionA64 106 /* Enable the SError interrupt */ 107 msr daifclr, #DAIF_ABT_BIT 108 109 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 110 111 /* Expect only SMC exceptions */ 112 mrs x30, esr_el3 113 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 114 cmp x30, #EC_AARCH64_SMC 115 b.ne unexpected_sync_exception 116 117 b smc_handler64 118 check_vector_size SynchronousExceptionA64 119 120vector_entry IrqA64 121 mov x0, #IRQ_AARCH64 122 bl plat_report_exception 123 b IrqA64 124 check_vector_size IrqA64 125 126vector_entry FiqA64 127 mov x0, #FIQ_AARCH64 128 bl plat_report_exception 129 b FiqA64 130 check_vector_size FiqA64 131 132vector_entry SErrorA64 133 mov x0, #SERROR_AARCH64 134 bl plat_report_exception 135 b SErrorA64 136 check_vector_size SErrorA64 137 138 /* ----------------------------------------------------- 139 * Lower EL using AArch32 : 0x600 - 0x800 140 * ----------------------------------------------------- 141 */ 142vector_entry SynchronousExceptionA32 143 mov x0, #SYNC_EXCEPTION_AARCH32 144 bl plat_report_exception 145 b SynchronousExceptionA32 146 check_vector_size SynchronousExceptionA32 147 148vector_entry IrqA32 149 mov x0, #IRQ_AARCH32 150 bl plat_report_exception 151 b IrqA32 152 check_vector_size IrqA32 153 154vector_entry FiqA32 155 mov x0, #FIQ_AARCH32 156 bl plat_report_exception 157 b FiqA32 158 check_vector_size FiqA32 159 160vector_entry SErrorA32 161 mov x0, #SERROR_AARCH32 162 bl plat_report_exception 163 b SErrorA32 164 check_vector_size SErrorA32 165 166 167func smc_handler64 168 169 /* ---------------------------------------------- 170 * Detect if this is a RUN_IMAGE or other SMC. 171 * ---------------------------------------------- 172 */ 173 mov x30, #BL1_SMC_RUN_IMAGE 174 cmp x30, x0 175 b.ne smc_handler 176 177 /* ------------------------------------------------ 178 * Make sure only Secure world reaches here. 179 * ------------------------------------------------ 180 */ 181 mrs x30, scr_el3 182 tst x30, #SCR_NS_BIT 183 b.ne unexpected_sync_exception 184 185 /* ---------------------------------------------- 186 * Handling RUN_IMAGE SMC. First switch back to 187 * SP_EL0 for the C runtime stack. 188 * ---------------------------------------------- 189 */ 190 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 191 msr spsel, #0 192 mov sp, x30 193 194 /* --------------------------------------------------------------------- 195 * Pass EL3 control to BL31. 196 * Here it expects X1 with the address of a entry_point_info_t 197 * structure describing the BL31 entrypoint. 198 * --------------------------------------------------------------------- 199 */ 200 mov x20, x1 201 202 mov x0, x20 203 bl bl1_print_bl31_ep_info 204 205 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 206 msr elr_el3, x0 207 msr spsr_el3, x1 208 ubfx x0, x1, #MODE_EL_SHIFT, #2 209 cmp x0, #MODE_EL3 210 b.ne unexpected_sync_exception 211 212 bl disable_mmu_icache_el3 213 tlbi alle3 214 215#if SPIN_ON_BL1_EXIT 216 bl print_debug_loop_message 217debug_loop: 218 b debug_loop 219#endif 220 221 mov x0, x20 222 bl bl1_plat_prepare_exit 223 224 ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 225 ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 226 ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 227 ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 228 eret 229endfunc smc_handler64 230 231unexpected_sync_exception: 232 mov x0, #SYNC_EXCEPTION_AARCH64 233 bl plat_report_exception 234 wfi 235 b unexpected_sync_exception 236 237 /* ----------------------------------------------------- 238 * Save Secure/Normal world context and jump to 239 * BL1 SMC handler. 240 * ----------------------------------------------------- 241 */ 242smc_handler: 243 /* ----------------------------------------------------- 244 * Save the GP registers x0-x29. 245 * TODO: Revisit to store only SMCC specified registers. 246 * ----------------------------------------------------- 247 */ 248 bl save_gp_registers 249 250 /* ----------------------------------------------------- 251 * Populate the parameters for the SMC handler. We 252 * already have x0-x4 in place. x5 will point to a 253 * cookie (not used now). x6 will point to the context 254 * structure (SP_EL3) and x7 will contain flags we need 255 * to pass to the handler. 256 * ----------------------------------------------------- 257 */ 258 mov x5, xzr 259 mov x6, sp 260 261 /* ----------------------------------------------------- 262 * Restore the saved C runtime stack value which will 263 * become the new SP_EL0 i.e. EL3 runtime stack. It was 264 * saved in the 'cpu_context' structure prior to the last 265 * ERET from EL3. 266 * ----------------------------------------------------- 267 */ 268 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 269 270 /* --------------------------------------------- 271 * Switch back to SP_EL0 for the C runtime stack. 272 * --------------------------------------------- 273 */ 274 msr spsel, #0 275 mov sp, x12 276 277 /* ----------------------------------------------------- 278 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there 279 * is a world switch during SMC handling. 280 * ----------------------------------------------------- 281 */ 282 mrs x16, spsr_el3 283 mrs x17, elr_el3 284 mrs x18, scr_el3 285 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 286 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 287 288 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 289 bfi x7, x18, #0, #1 290 291 /* ----------------------------------------------------- 292 * Go to BL1 SMC handler. 293 * ----------------------------------------------------- 294 */ 295 bl bl1_smc_handler 296 297 /* ----------------------------------------------------- 298 * Do the transition to next BL image. 299 * ----------------------------------------------------- 300 */ 301 b el3_exit 302