1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <bl_common.h> 33#include <bl1.h> 34#include <platform.h> 35#include <runtime_svc.h> 36#include <asm_macros.S> 37 38 .globl bl1_exceptions 39 40 .section .vectors, "ax"; .align 11 41 42 /* ----------------------------------------------------- 43 * Very simple stackless exception handlers used by BL1. 44 * ----------------------------------------------------- 45 */ 46 .align 7 47bl1_exceptions: 48 /* ----------------------------------------------------- 49 * Current EL with SP0 : 0x0 - 0x180 50 * ----------------------------------------------------- 51 */ 52SynchronousExceptionSP0: 53 mov x0, #SYNC_EXCEPTION_SP_EL0 54 bl plat_report_exception 55 b SynchronousExceptionSP0 56 check_vector_size SynchronousExceptionSP0 57 58 .align 7 59IrqSP0: 60 mov x0, #IRQ_SP_EL0 61 bl plat_report_exception 62 b IrqSP0 63 check_vector_size IrqSP0 64 65 .align 7 66FiqSP0: 67 mov x0, #FIQ_SP_EL0 68 bl plat_report_exception 69 b FiqSP0 70 check_vector_size FiqSP0 71 72 .align 7 73SErrorSP0: 74 mov x0, #SERROR_SP_EL0 75 bl plat_report_exception 76 b SErrorSP0 77 check_vector_size SErrorSP0 78 79 /* ----------------------------------------------------- 80 * Current EL with SPx: 0x200 - 0x380 81 * ----------------------------------------------------- 82 */ 83 .align 7 84SynchronousExceptionSPx: 85 mov x0, #SYNC_EXCEPTION_SP_ELX 86 bl plat_report_exception 87 b SynchronousExceptionSPx 88 check_vector_size SynchronousExceptionSPx 89 90 .align 7 91IrqSPx: 92 mov x0, #IRQ_SP_ELX 93 bl plat_report_exception 94 b IrqSPx 95 check_vector_size IrqSPx 96 97 .align 7 98FiqSPx: 99 mov x0, #FIQ_SP_ELX 100 bl plat_report_exception 101 b FiqSPx 102 check_vector_size FiqSPx 103 104 .align 7 105SErrorSPx: 106 mov x0, #SERROR_SP_ELX 107 bl plat_report_exception 108 b SErrorSPx 109 check_vector_size SErrorSPx 110 111 /* ----------------------------------------------------- 112 * Lower EL using AArch64 : 0x400 - 0x580 113 * ----------------------------------------------------- 114 */ 115 .align 7 116SynchronousExceptionA64: 117 /* --------------------------------------------- 118 * Only a single SMC exception from BL2 to ask 119 * BL1 to pass EL3 control to BL31 is expected 120 * here. 121 * --------------------------------------------- 122 */ 123 b process_exception 124 check_vector_size SynchronousExceptionA64 125 126 .align 7 127IrqA64: 128 mov x0, #IRQ_AARCH64 129 bl plat_report_exception 130 b IrqA64 131 check_vector_size IrqA64 132 133 .align 7 134FiqA64: 135 mov x0, #FIQ_AARCH64 136 bl plat_report_exception 137 b FiqA64 138 check_vector_size FiqA64 139 140 .align 7 141SErrorA64: 142 mov x0, #SERROR_AARCH64 143 bl plat_report_exception 144 b SErrorA64 145 check_vector_size SErrorA64 146 147 /* ----------------------------------------------------- 148 * Lower EL using AArch32 : 0x0 - 0x180 149 * ----------------------------------------------------- 150 */ 151 .align 7 152SynchronousExceptionA32: 153 mov x0, #SYNC_EXCEPTION_AARCH32 154 bl plat_report_exception 155 b SynchronousExceptionA32 156 check_vector_size SynchronousExceptionA32 157 158 .align 7 159IrqA32: 160 mov x0, #IRQ_AARCH32 161 bl plat_report_exception 162 b IrqA32 163 check_vector_size IrqA32 164 165 .align 7 166FiqA32: 167 mov x0, #FIQ_AARCH32 168 bl plat_report_exception 169 b FiqA32 170 check_vector_size FiqA32 171 172 .align 7 173SErrorA32: 174 mov x0, #SERROR_AARCH32 175 bl plat_report_exception 176 b SErrorA32 177 check_vector_size SErrorA32 178 179 .align 7 180 181func process_exception 182 sub sp, sp, #0x40 183 stp x0, x1, [sp, #0x0] 184 stp x2, x3, [sp, #0x10] 185 stp x4, x5, [sp, #0x20] 186 stp x6, x7, [sp, #0x30] 187 188 mov x19, x0 189 mov x20, x1 190 mov x21, x2 191 mov x0, #SYNC_EXCEPTION_AARCH64 192 bl plat_report_exception 193 194 bl read_esr_el3 195 ubfx x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH 196 cmp x1, #EC_AARCH64_SMC 197 b.ne panic 198 mov x1, #RUN_IMAGE 199 cmp x19, x1 200 b.ne panic 201 mov x0, x20 202 mov x1, x21 203 mov x2, x3 204 mov x3, x4 205 bl display_boot_progress 206 mov x0, x20 207 bl write_elr 208 mov x0, x21 209 bl write_spsr 210 ubfx x0, x21, #MODE_EL_SHIFT, #2 211 cmp x0, #MODE_EL3 212 b.ne skip_mmu_teardown 213 214 /* --------------------------------------------- 215 * If BL31 is to be executed in EL3 as well 216 * then turn off the MMU so that it can perform 217 * its own setup. TODO: Assuming flat mapped 218 * translations here. Also all should go into a 219 * separate MMU teardown function 220 * --------------------------------------------- 221 */ 222 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) 223 bl read_sctlr_el3 224 bic x0, x0, x1 225 bl write_sctlr_el3 226 mov x0, #DCCISW 227 bl dcsw_op_all 228 bl tlbialle3 229skip_mmu_teardown: 230 ldp x6, x7, [sp, #0x30] 231 ldp x4, x5, [sp, #0x20] 232 ldp x2, x3, [sp, #0x10] 233 ldp x0, x1, [sp, #0x0] 234 add sp, sp, #0x40 235 eret 236 237panic: 238 wfi 239 b panic 240