16c595b3dSSandrine Bailleux/* 2e0ae9fabSSandrine Bailleux * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 36c595b3dSSandrine Bailleux * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 56c595b3dSSandrine Bailleux */ 66c595b3dSSandrine Bailleux 76c595b3dSSandrine Bailleux#include <arch.h> 86c595b3dSSandrine Bailleux#include <asm_macros.S> 948bfb88eSYatharth Kochar#include <bl1.h> 102a4b4b71SIsla Mitchell#include <bl_common.h> 117baff11fSYatharth Kochar#include <context.h> 126c595b3dSSandrine Bailleux 13e0ae9fabSSandrine Bailleux/* ----------------------------------------------------------------------------- 14e0ae9fabSSandrine Bailleux * Very simple stackless exception handlers used by BL1. 15e0ae9fabSSandrine Bailleux * ----------------------------------------------------------------------------- 16e0ae9fabSSandrine Bailleux */ 176c595b3dSSandrine Bailleux .globl bl1_exceptions 186c595b3dSSandrine Bailleux 19e0ae9fabSSandrine Bailleuxvector_base bl1_exceptions 206c595b3dSSandrine Bailleux 216c595b3dSSandrine Bailleux /* ----------------------------------------------------- 2244804252SSandrine Bailleux * Current EL with SP0 : 0x0 - 0x200 236c595b3dSSandrine Bailleux * ----------------------------------------------------- 246c595b3dSSandrine Bailleux */ 25e0ae9fabSSandrine Bailleuxvector_entry SynchronousExceptionSP0 266c595b3dSSandrine Bailleux mov x0, #SYNC_EXCEPTION_SP_EL0 276c595b3dSSandrine Bailleux bl plat_report_exception 28a806dad5SJeenu Viswambharan no_ret plat_panic_handler 296c595b3dSSandrine Bailleux check_vector_size SynchronousExceptionSP0 306c595b3dSSandrine Bailleux 31e0ae9fabSSandrine Bailleuxvector_entry IrqSP0 326c595b3dSSandrine Bailleux mov x0, #IRQ_SP_EL0 336c595b3dSSandrine Bailleux bl plat_report_exception 34a806dad5SJeenu Viswambharan no_ret plat_panic_handler 356c595b3dSSandrine Bailleux check_vector_size IrqSP0 366c595b3dSSandrine Bailleux 37e0ae9fabSSandrine Bailleuxvector_entry FiqSP0 386c595b3dSSandrine Bailleux mov x0, #FIQ_SP_EL0 396c595b3dSSandrine Bailleux bl plat_report_exception 40a806dad5SJeenu Viswambharan no_ret plat_panic_handler 416c595b3dSSandrine Bailleux check_vector_size FiqSP0 426c595b3dSSandrine Bailleux 43e0ae9fabSSandrine Bailleuxvector_entry SErrorSP0 446c595b3dSSandrine Bailleux mov x0, #SERROR_SP_EL0 456c595b3dSSandrine Bailleux bl plat_report_exception 46a806dad5SJeenu Viswambharan no_ret plat_panic_handler 476c595b3dSSandrine Bailleux check_vector_size SErrorSP0 486c595b3dSSandrine Bailleux 496c595b3dSSandrine Bailleux /* ----------------------------------------------------- 5044804252SSandrine Bailleux * Current EL with SPx: 0x200 - 0x400 516c595b3dSSandrine Bailleux * ----------------------------------------------------- 526c595b3dSSandrine Bailleux */ 53e0ae9fabSSandrine Bailleuxvector_entry SynchronousExceptionSPx 546c595b3dSSandrine Bailleux mov x0, #SYNC_EXCEPTION_SP_ELX 556c595b3dSSandrine Bailleux bl plat_report_exception 56a806dad5SJeenu Viswambharan no_ret plat_panic_handler 576c595b3dSSandrine Bailleux check_vector_size SynchronousExceptionSPx 586c595b3dSSandrine Bailleux 59e0ae9fabSSandrine Bailleuxvector_entry IrqSPx 606c595b3dSSandrine Bailleux mov x0, #IRQ_SP_ELX 616c595b3dSSandrine Bailleux bl plat_report_exception 62a806dad5SJeenu Viswambharan no_ret plat_panic_handler 636c595b3dSSandrine Bailleux check_vector_size IrqSPx 646c595b3dSSandrine Bailleux 65e0ae9fabSSandrine Bailleuxvector_entry FiqSPx 666c595b3dSSandrine Bailleux mov x0, #FIQ_SP_ELX 676c595b3dSSandrine Bailleux bl plat_report_exception 68a806dad5SJeenu Viswambharan no_ret plat_panic_handler 696c595b3dSSandrine Bailleux check_vector_size FiqSPx 706c595b3dSSandrine Bailleux 71e0ae9fabSSandrine Bailleuxvector_entry SErrorSPx 726c595b3dSSandrine Bailleux mov x0, #SERROR_SP_ELX 736c595b3dSSandrine Bailleux bl plat_report_exception 74a806dad5SJeenu Viswambharan no_ret plat_panic_handler 756c595b3dSSandrine Bailleux check_vector_size SErrorSPx 766c595b3dSSandrine Bailleux 776c595b3dSSandrine Bailleux /* ----------------------------------------------------- 7844804252SSandrine Bailleux * Lower EL using AArch64 : 0x400 - 0x600 796c595b3dSSandrine Bailleux * ----------------------------------------------------- 806c595b3dSSandrine Bailleux */ 81e0ae9fabSSandrine Bailleuxvector_entry SynchronousExceptionA64 820c8d4fefSAchin Gupta /* Enable the SError interrupt */ 830c8d4fefSAchin Gupta msr daifclr, #DAIF_ABT_BIT 840c8d4fefSAchin Gupta 857baff11fSYatharth Kochar str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 867baff11fSYatharth Kochar 871fe4d453SSandrine Bailleux /* Expect only SMC exceptions */ 887baff11fSYatharth Kochar mrs x30, esr_el3 897baff11fSYatharth Kochar ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 907baff11fSYatharth Kochar cmp x30, #EC_AARCH64_SMC 911fe4d453SSandrine Bailleux b.ne unexpected_sync_exception 9229fb905dSVikram Kanigiri 931fe4d453SSandrine Bailleux b smc_handler64 946c595b3dSSandrine Bailleux check_vector_size SynchronousExceptionA64 956c595b3dSSandrine Bailleux 96e0ae9fabSSandrine Bailleuxvector_entry IrqA64 976c595b3dSSandrine Bailleux mov x0, #IRQ_AARCH64 986c595b3dSSandrine Bailleux bl plat_report_exception 99a806dad5SJeenu Viswambharan no_ret plat_panic_handler 1006c595b3dSSandrine Bailleux check_vector_size IrqA64 1016c595b3dSSandrine Bailleux 102e0ae9fabSSandrine Bailleuxvector_entry FiqA64 1036c595b3dSSandrine Bailleux mov x0, #FIQ_AARCH64 1046c595b3dSSandrine Bailleux bl plat_report_exception 105a806dad5SJeenu Viswambharan no_ret plat_panic_handler 1066c595b3dSSandrine Bailleux check_vector_size FiqA64 1076c595b3dSSandrine Bailleux 108e0ae9fabSSandrine Bailleuxvector_entry SErrorA64 1096c595b3dSSandrine Bailleux mov x0, #SERROR_AARCH64 1106c595b3dSSandrine Bailleux bl plat_report_exception 111a806dad5SJeenu Viswambharan no_ret plat_panic_handler 1126c595b3dSSandrine Bailleux check_vector_size SErrorA64 1136c595b3dSSandrine Bailleux 1146c595b3dSSandrine Bailleux /* ----------------------------------------------------- 11544804252SSandrine Bailleux * Lower EL using AArch32 : 0x600 - 0x800 1166c595b3dSSandrine Bailleux * ----------------------------------------------------- 1176c595b3dSSandrine Bailleux */ 118e0ae9fabSSandrine Bailleuxvector_entry SynchronousExceptionA32 1196c595b3dSSandrine Bailleux mov x0, #SYNC_EXCEPTION_AARCH32 1206c595b3dSSandrine Bailleux bl plat_report_exception 121a806dad5SJeenu Viswambharan no_ret plat_panic_handler 1226c595b3dSSandrine Bailleux check_vector_size SynchronousExceptionA32 1236c595b3dSSandrine Bailleux 124e0ae9fabSSandrine Bailleuxvector_entry IrqA32 1256c595b3dSSandrine Bailleux mov x0, #IRQ_AARCH32 1266c595b3dSSandrine Bailleux bl plat_report_exception 127a806dad5SJeenu Viswambharan no_ret plat_panic_handler 1286c595b3dSSandrine Bailleux check_vector_size IrqA32 1296c595b3dSSandrine Bailleux 130e0ae9fabSSandrine Bailleuxvector_entry FiqA32 1316c595b3dSSandrine Bailleux mov x0, #FIQ_AARCH32 1326c595b3dSSandrine Bailleux bl plat_report_exception 133a806dad5SJeenu Viswambharan no_ret plat_panic_handler 1346c595b3dSSandrine Bailleux check_vector_size FiqA32 1356c595b3dSSandrine Bailleux 136e0ae9fabSSandrine Bailleuxvector_entry SErrorA32 1376c595b3dSSandrine Bailleux mov x0, #SERROR_AARCH32 1386c595b3dSSandrine Bailleux bl plat_report_exception 139a806dad5SJeenu Viswambharan no_ret plat_panic_handler 1406c595b3dSSandrine Bailleux check_vector_size SErrorA32 1411fe4d453SSandrine Bailleux 1421fe4d453SSandrine Bailleux 1431fe4d453SSandrine Bailleuxfunc smc_handler64 14448bfb88eSYatharth Kochar 1457baff11fSYatharth Kochar /* ---------------------------------------------- 14648bfb88eSYatharth Kochar * Detect if this is a RUN_IMAGE or other SMC. 14748bfb88eSYatharth Kochar * ---------------------------------------------- 14848bfb88eSYatharth Kochar */ 14948bfb88eSYatharth Kochar mov x30, #BL1_SMC_RUN_IMAGE 15048bfb88eSYatharth Kochar cmp x30, x0 15148bfb88eSYatharth Kochar b.ne smc_handler 15248bfb88eSYatharth Kochar 15348bfb88eSYatharth Kochar /* ------------------------------------------------ 15448bfb88eSYatharth Kochar * Make sure only Secure world reaches here. 15548bfb88eSYatharth Kochar * ------------------------------------------------ 15648bfb88eSYatharth Kochar */ 15748bfb88eSYatharth Kochar mrs x30, scr_el3 15848bfb88eSYatharth Kochar tst x30, #SCR_NS_BIT 15948bfb88eSYatharth Kochar b.ne unexpected_sync_exception 16048bfb88eSYatharth Kochar 16148bfb88eSYatharth Kochar /* ---------------------------------------------- 16248bfb88eSYatharth Kochar * Handling RUN_IMAGE SMC. First switch back to 16348bfb88eSYatharth Kochar * SP_EL0 for the C runtime stack. 1647baff11fSYatharth Kochar * ---------------------------------------------- 1657baff11fSYatharth Kochar */ 1667baff11fSYatharth Kochar ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 1677baff11fSYatharth Kochar msr spsel, #0 1687baff11fSYatharth Kochar mov sp, x30 1697baff11fSYatharth Kochar 1701fe4d453SSandrine Bailleux /* --------------------------------------------------------------------- 171f3b4914bSYatharth Kochar * Pass EL3 control to next BL image. 17248bfb88eSYatharth Kochar * Here it expects X1 with the address of a entry_point_info_t 173f3b4914bSYatharth Kochar * structure describing the next BL image entrypoint. 1741fe4d453SSandrine Bailleux * --------------------------------------------------------------------- 1751fe4d453SSandrine Bailleux */ 1761fe4d453SSandrine Bailleux mov x20, x1 1771fe4d453SSandrine Bailleux 1781fe4d453SSandrine Bailleux mov x0, x20 179f3b4914bSYatharth Kochar bl bl1_print_next_bl_ep_info 1801fe4d453SSandrine Bailleux 1811fe4d453SSandrine Bailleux ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 1821fe4d453SSandrine Bailleux msr elr_el3, x0 1831fe4d453SSandrine Bailleux msr spsr_el3, x1 1841fe4d453SSandrine Bailleux ubfx x0, x1, #MODE_EL_SHIFT, #2 1851fe4d453SSandrine Bailleux cmp x0, #MODE_EL3 1861fe4d453SSandrine Bailleux b.ne unexpected_sync_exception 1871fe4d453SSandrine Bailleux 1881fe4d453SSandrine Bailleux bl disable_mmu_icache_el3 1891fe4d453SSandrine Bailleux tlbi alle3 190*6bf0e079SAntonio Nino Diaz dsb ish /* ERET implies ISB, so it is not needed here */ 1911fe4d453SSandrine Bailleux 19235e8c766SSandrine Bailleux#if SPIN_ON_BL1_EXIT 19335e8c766SSandrine Bailleux bl print_debug_loop_message 19435e8c766SSandrine Bailleuxdebug_loop: 19535e8c766SSandrine Bailleux b debug_loop 19635e8c766SSandrine Bailleux#endif 19735e8c766SSandrine Bailleux 198862b5dc2SSandrine Bailleux mov x0, x20 199e3f67124SJuan Castillo bl bl1_plat_prepare_exit 200e3f67124SJuan Castillo 2011fe4d453SSandrine Bailleux ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 2021fe4d453SSandrine Bailleux ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 2031fe4d453SSandrine Bailleux ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 2041fe4d453SSandrine Bailleux ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 2051fe4d453SSandrine Bailleux eret 2061fe4d453SSandrine Bailleuxendfunc smc_handler64 2071fe4d453SSandrine Bailleux 2081fe4d453SSandrine Bailleuxunexpected_sync_exception: 2091fe4d453SSandrine Bailleux mov x0, #SYNC_EXCEPTION_AARCH64 2101fe4d453SSandrine Bailleux bl plat_report_exception 211a806dad5SJeenu Viswambharan no_ret plat_panic_handler 21248bfb88eSYatharth Kochar 21348bfb88eSYatharth Kochar /* ----------------------------------------------------- 21448bfb88eSYatharth Kochar * Save Secure/Normal world context and jump to 21548bfb88eSYatharth Kochar * BL1 SMC handler. 21648bfb88eSYatharth Kochar * ----------------------------------------------------- 21748bfb88eSYatharth Kochar */ 21848bfb88eSYatharth Kocharsmc_handler: 21948bfb88eSYatharth Kochar /* ----------------------------------------------------- 22048bfb88eSYatharth Kochar * Save the GP registers x0-x29. 22148bfb88eSYatharth Kochar * TODO: Revisit to store only SMCC specified registers. 22248bfb88eSYatharth Kochar * ----------------------------------------------------- 22348bfb88eSYatharth Kochar */ 22448bfb88eSYatharth Kochar bl save_gp_registers 22548bfb88eSYatharth Kochar 22648bfb88eSYatharth Kochar /* ----------------------------------------------------- 22748bfb88eSYatharth Kochar * Populate the parameters for the SMC handler. We 22848bfb88eSYatharth Kochar * already have x0-x4 in place. x5 will point to a 22948bfb88eSYatharth Kochar * cookie (not used now). x6 will point to the context 23048bfb88eSYatharth Kochar * structure (SP_EL3) and x7 will contain flags we need 23148bfb88eSYatharth Kochar * to pass to the handler. 23248bfb88eSYatharth Kochar * ----------------------------------------------------- 23348bfb88eSYatharth Kochar */ 23448bfb88eSYatharth Kochar mov x5, xzr 23548bfb88eSYatharth Kochar mov x6, sp 23648bfb88eSYatharth Kochar 23748bfb88eSYatharth Kochar /* ----------------------------------------------------- 23848bfb88eSYatharth Kochar * Restore the saved C runtime stack value which will 23948bfb88eSYatharth Kochar * become the new SP_EL0 i.e. EL3 runtime stack. It was 24048bfb88eSYatharth Kochar * saved in the 'cpu_context' structure prior to the last 24148bfb88eSYatharth Kochar * ERET from EL3. 24248bfb88eSYatharth Kochar * ----------------------------------------------------- 24348bfb88eSYatharth Kochar */ 24448bfb88eSYatharth Kochar ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 24548bfb88eSYatharth Kochar 24648bfb88eSYatharth Kochar /* --------------------------------------------- 24748bfb88eSYatharth Kochar * Switch back to SP_EL0 for the C runtime stack. 24848bfb88eSYatharth Kochar * --------------------------------------------- 24948bfb88eSYatharth Kochar */ 25048bfb88eSYatharth Kochar msr spsel, #0 25148bfb88eSYatharth Kochar mov sp, x12 25248bfb88eSYatharth Kochar 25348bfb88eSYatharth Kochar /* ----------------------------------------------------- 25448bfb88eSYatharth Kochar * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there 25548bfb88eSYatharth Kochar * is a world switch during SMC handling. 25648bfb88eSYatharth Kochar * ----------------------------------------------------- 25748bfb88eSYatharth Kochar */ 25848bfb88eSYatharth Kochar mrs x16, spsr_el3 25948bfb88eSYatharth Kochar mrs x17, elr_el3 26048bfb88eSYatharth Kochar mrs x18, scr_el3 26148bfb88eSYatharth Kochar stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 26248bfb88eSYatharth Kochar str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 26348bfb88eSYatharth Kochar 26448bfb88eSYatharth Kochar /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 26548bfb88eSYatharth Kochar bfi x7, x18, #0, #1 26648bfb88eSYatharth Kochar 26748bfb88eSYatharth Kochar /* ----------------------------------------------------- 26848bfb88eSYatharth Kochar * Go to BL1 SMC handler. 26948bfb88eSYatharth Kochar * ----------------------------------------------------- 27048bfb88eSYatharth Kochar */ 27148bfb88eSYatharth Kochar bl bl1_smc_handler 27248bfb88eSYatharth Kochar 27348bfb88eSYatharth Kochar /* ----------------------------------------------------- 27448bfb88eSYatharth Kochar * Do the transition to next BL image. 27548bfb88eSYatharth Kochar * ----------------------------------------------------- 27648bfb88eSYatharth Kochar */ 27748bfb88eSYatharth Kochar b el3_exit 278