1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33 34 .globl bl1_entrypoint 35 36 37 /* ----------------------------------------------------- 38 * bl1_entrypoint() is the entry point into the trusted 39 * firmware code when a cpu is released from warm or 40 * cold reset. 41 * ----------------------------------------------------- 42 */ 43 44func bl1_entrypoint 45 /* --------------------------------------------- 46 * Set the CPU endianness before doing anything 47 * that might involve memory reads or writes. 48 * --------------------------------------------- 49 */ 50 mrs x0, sctlr_el3 51 bic x0, x0, #SCTLR_EE_BIT 52 msr sctlr_el3, x0 53 isb 54 55 /* --------------------------------------------- 56 * Perform any processor specific actions upon 57 * reset e.g. cache, tlb invalidations etc. 58 * --------------------------------------------- 59 */ 60 bl cpu_reset_handler 61 62 /* --------------------------------------------- 63 * Enable the instruction cache, stack pointer 64 * and data access alignment checks 65 * --------------------------------------------- 66 */ 67 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 68 mrs x0, sctlr_el3 69 orr x0, x0, x1 70 msr sctlr_el3, x0 71 isb 72 73 /* --------------------------------------------- 74 * Set the exception vector to something sane. 75 * --------------------------------------------- 76 */ 77 adr x0, bl1_exceptions 78 msr vbar_el3, x0 79 80 /* --------------------------------------------------------------------- 81 * The initial state of the Architectural feature trap register 82 * (CPTR_EL3) is unknown and it must be set to a known state. All 83 * feature traps are disabled. Some bits in this register are marked as 84 * Reserved and should not be modified. 85 * 86 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 87 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. 88 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap 89 * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register 90 * access to trace functionality is not supported, this bit is RES0. 91 * CPTR_EL3.TFP: This causes instructions that access the registers 92 * associated with Floating Point and Advanced SIMD execution to trap 93 * to EL3 when executed from any exception level, unless trapped to EL1 94 * or EL2. 95 * --------------------------------------------------------------------- 96 */ 97 mrs x0, cptr_el3 98 bic w0, w0, #TCPAC_BIT 99 bic w0, w0, #TTA_BIT 100 bic w0, w0, #TFP_BIT 101 msr cptr_el3, x0 102 103 /* ------------------------------------------------------- 104 * Will not return from this macro if it is a warm boot. 105 * ------------------------------------------------------- 106 */ 107 wait_for_entrypoint 108 109 bl platform_mem_init 110 111 /* --------------------------------------------- 112 * Init C runtime environment. 113 * - Zero-initialise the NOBITS sections. 114 * There are 2 of them: 115 * - the .bss section; 116 * - the coherent memory section. 117 * - Copy the data section from BL1 image 118 * (stored in ROM) to the correct location 119 * in RAM. 120 * --------------------------------------------- 121 */ 122 ldr x0, =__BSS_START__ 123 ldr x1, =__BSS_SIZE__ 124 bl zeromem16 125 126 ldr x0, =__COHERENT_RAM_START__ 127 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 128 bl zeromem16 129 130 ldr x0, =__DATA_RAM_START__ 131 ldr x1, =__DATA_ROM_START__ 132 ldr x2, =__DATA_SIZE__ 133 bl memcpy16 134 135 /* -------------------------------------------- 136 * Allocate a stack whose memory will be marked 137 * as Normal-IS-WBWA when the MMU is enabled. 138 * There is no risk of reading stale stack 139 * memory after enabling the MMU as only the 140 * primary cpu is running at the moment. 141 * -------------------------------------------- 142 */ 143 mrs x0, mpidr_el1 144 bl platform_set_stack 145 146 /* --------------------------------------------- 147 * Architectural init. can be generic e.g. 148 * enabling stack alignment and platform spec- 149 * ific e.g. MMU & page table setup as per the 150 * platform memory map. Perform the latter here 151 * and the former in bl1_main. 152 * --------------------------------------------- 153 */ 154 bl bl1_early_platform_setup 155 bl bl1_plat_arch_setup 156 157 /* -------------------------------------------------- 158 * Initialize platform and jump to our c-entry point 159 * for this type of reset. Panic if it returns 160 * -------------------------------------------------- 161 */ 162 bl bl1_main 163panic: 164 b panic 165