1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32 33 .globl reset_handler 34 35 36 .section .text, "ax"; .align 3 37 38 /* ----------------------------------------------------- 39 * reset_handler() is the entry point into the trusted 40 * firmware code when a cpu is released from warm or 41 * cold reset. 42 * ----------------------------------------------------- 43 */ 44 45reset_handler: ; .type reset_handler, %function 46 /* --------------------------------------------- 47 * Perform any processor specific actions upon 48 * reset e.g. cache, tlb invalidations etc. 49 * --------------------------------------------- 50 */ 51 bl cpu_reset_handler 52 53 /* --------------------------------------------- 54 * Set the exception vector to something sane. 55 * --------------------------------------------- 56 */ 57 adr x0, early_exceptions 58 msr vbar_el3, x0 59 60 /* --------------------------------------------------------------------- 61 * The initial state of the Architectural feature trap register 62 * (CPTR_EL3) is unknown and it must be set to a known state. All 63 * feature traps are disabled. Some bits in this register are marked as 64 * Reserved and should not be modified. 65 * 66 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 67 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. 68 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap 69 * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register 70 * access to trace functionality is not supported, this bit is RES0. 71 * CPTR_EL3.TFP: This causes instructions that access the registers 72 * associated with Floating Point and Advanced SIMD execution to trap 73 * to EL3 when executed from any exception level, unless trapped to EL1 74 * or EL2. 75 * --------------------------------------------------------------------- 76 */ 77 mrs x0, cptr_el3 78 bic w0, w0, #TCPAC_BIT 79 bic w0, w0, #TTA_BIT 80 bic w0, w0, #TFP_BIT 81 msr cptr_el3, x0 82 83 /* --------------------------------------------- 84 * Enable the instruction cache. 85 * --------------------------------------------- 86 */ 87 mrs x0, sctlr_el3 88 orr x0, x0, #SCTLR_I_BIT 89 msr sctlr_el3, x0 90 91 isb 92 93_wait_for_entrypoint: 94 /* --------------------------------------------- 95 * Find the type of reset and jump to handler 96 * if present. If the handler is null then it is 97 * a cold boot. The primary cpu will set up the 98 * platform while the secondaries wait for 99 * their turn to be woken up 100 * --------------------------------------------- 101 */ 102 bl read_mpidr 103 bl platform_get_entrypoint 104 cbnz x0, _do_warm_boot 105 bl read_mpidr 106 bl platform_is_primary_cpu 107 cbnz x0, _do_cold_boot 108 109 /* --------------------------------------------- 110 * Perform any platform specific secondary cpu 111 * actions 112 * --------------------------------------------- 113 */ 114 bl plat_secondary_cold_boot_setup 115 b _wait_for_entrypoint 116 117_do_cold_boot: 118 /* --------------------------------------------- 119 * Init C runtime environment. 120 * - Zero-initialise the NOBITS sections. 121 * There are 2 of them: 122 * - the .bss section; 123 * - the coherent memory section. 124 * - Copy the data section from BL1 image 125 * (stored in ROM) to the correct location 126 * in RAM. 127 * --------------------------------------------- 128 */ 129 ldr x0, =__BSS_START__ 130 ldr x1, =__BSS_SIZE__ 131 bl zeromem16 132 133 ldr x0, =__COHERENT_RAM_START__ 134 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 135 bl zeromem16 136 137 ldr x0, =__DATA_RAM_START__ 138 ldr x1, =__DATA_ROM_START__ 139 ldr x2, =__DATA_SIZE__ 140 bl memcpy16 141 142 /* --------------------------------------------- 143 * Initialize platform and jump to our c-entry 144 * point for this type of reset 145 * --------------------------------------------- 146 */ 147 adr x0, bl1_main 148 bl platform_cold_boot_init 149 b _panic 150 151_do_warm_boot: 152 /* --------------------------------------------- 153 * Jump to BL31 for all warm boot init. 154 * --------------------------------------------- 155 */ 156 blr x0 157_panic: 158 b _panic 159