14f6ad66aSAchin Gupta/* 2*e83b0cadSDan Handley * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 34f6ad66aSAchin Gupta * 44f6ad66aSAchin Gupta * Redistribution and use in source and binary forms, with or without 54f6ad66aSAchin Gupta * modification, are permitted provided that the following conditions are met: 64f6ad66aSAchin Gupta * 74f6ad66aSAchin Gupta * Redistributions of source code must retain the above copyright notice, this 84f6ad66aSAchin Gupta * list of conditions and the following disclaimer. 94f6ad66aSAchin Gupta * 104f6ad66aSAchin Gupta * Redistributions in binary form must reproduce the above copyright notice, 114f6ad66aSAchin Gupta * this list of conditions and the following disclaimer in the documentation 124f6ad66aSAchin Gupta * and/or other materials provided with the distribution. 134f6ad66aSAchin Gupta * 144f6ad66aSAchin Gupta * Neither the name of ARM nor the names of its contributors may be used 154f6ad66aSAchin Gupta * to endorse or promote products derived from this software without specific 164f6ad66aSAchin Gupta * prior written permission. 174f6ad66aSAchin Gupta * 184f6ad66aSAchin Gupta * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 194f6ad66aSAchin Gupta * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 204f6ad66aSAchin Gupta * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 214f6ad66aSAchin Gupta * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 224f6ad66aSAchin Gupta * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 234f6ad66aSAchin Gupta * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 244f6ad66aSAchin Gupta * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 254f6ad66aSAchin Gupta * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 264f6ad66aSAchin Gupta * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 274f6ad66aSAchin Gupta * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 284f6ad66aSAchin Gupta * POSSIBILITY OF SUCH DAMAGE. 294f6ad66aSAchin Gupta */ 304f6ad66aSAchin Gupta 31c10bd2ceSSandrine Bailleux#include <arch.h> 324f6ad66aSAchin Gupta 334f6ad66aSAchin Gupta .globl reset_handler 344f6ad66aSAchin Gupta 354f6ad66aSAchin Gupta 368d69a03fSSandrine Bailleux .section .text, "ax"; .align 3 374f6ad66aSAchin Gupta 384f6ad66aSAchin Gupta /* ----------------------------------------------------- 394f6ad66aSAchin Gupta * reset_handler() is the entry point into the trusted 404f6ad66aSAchin Gupta * firmware code when a cpu is released from warm or 414f6ad66aSAchin Gupta * cold reset. 424f6ad66aSAchin Gupta * ----------------------------------------------------- 434f6ad66aSAchin Gupta */ 444f6ad66aSAchin Gupta 454f6ad66aSAchin Guptareset_handler:; .type reset_handler, %function 464f6ad66aSAchin Gupta /* --------------------------------------------- 474f6ad66aSAchin Gupta * Perform any processor specific actions upon 484f6ad66aSAchin Gupta * reset e.g. cache, tlb invalidations etc. 494f6ad66aSAchin Gupta * --------------------------------------------- 504f6ad66aSAchin Gupta */ 514f6ad66aSAchin Gupta bl cpu_reset_handler 524f6ad66aSAchin Gupta 53c10bd2ceSSandrine Bailleux /* --------------------------------------------- 54c10bd2ceSSandrine Bailleux * Set the exception vector to something sane. 55c10bd2ceSSandrine Bailleux * --------------------------------------------- 56c10bd2ceSSandrine Bailleux */ 57c10bd2ceSSandrine Bailleux adr x0, early_exceptions 58c10bd2ceSSandrine Bailleux msr vbar_el3, x0 59c10bd2ceSSandrine Bailleux 60c10bd2ceSSandrine Bailleux /* --------------------------------------------- 61c10bd2ceSSandrine Bailleux * Enable the instruction cache. 62c10bd2ceSSandrine Bailleux * --------------------------------------------- 63c10bd2ceSSandrine Bailleux */ 64c10bd2ceSSandrine Bailleux mrs x0, sctlr_el3 65c10bd2ceSSandrine Bailleux orr x0, x0, #SCTLR_I_BIT 66c10bd2ceSSandrine Bailleux msr sctlr_el3, x0 67c10bd2ceSSandrine Bailleux 68c10bd2ceSSandrine Bailleux isb 69c10bd2ceSSandrine Bailleux 704f6ad66aSAchin Gupta_wait_for_entrypoint: 714f6ad66aSAchin Gupta /* --------------------------------------------- 724f6ad66aSAchin Gupta * Find the type of reset and jump to handler 734f6ad66aSAchin Gupta * if present. If the handler is null then it is 744f6ad66aSAchin Gupta * a cold boot. The primary cpu will set up the 754f6ad66aSAchin Gupta * platform while the secondaries wait for 764f6ad66aSAchin Gupta * their turn to be woken up 774f6ad66aSAchin Gupta * --------------------------------------------- 784f6ad66aSAchin Gupta */ 794f6ad66aSAchin Gupta bl read_mpidr 804f6ad66aSAchin Gupta bl platform_get_entrypoint 814f6ad66aSAchin Gupta cbnz x0, _do_warm_boot 824f6ad66aSAchin Gupta bl read_mpidr 834f6ad66aSAchin Gupta bl platform_is_primary_cpu 844f6ad66aSAchin Gupta cbnz x0, _do_cold_boot 854f6ad66aSAchin Gupta 864f6ad66aSAchin Gupta /* --------------------------------------------- 874f6ad66aSAchin Gupta * Perform any platform specific secondary cpu 884f6ad66aSAchin Gupta * actions 894f6ad66aSAchin Gupta * --------------------------------------------- 904f6ad66aSAchin Gupta */ 914f6ad66aSAchin Gupta bl plat_secondary_cold_boot_setup 924f6ad66aSAchin Gupta b _wait_for_entrypoint 934f6ad66aSAchin Gupta 944f6ad66aSAchin Gupta_do_cold_boot: 954f6ad66aSAchin Gupta /* --------------------------------------------- 9665f546a1SSandrine Bailleux * Init C runtime environment. 9765f546a1SSandrine Bailleux * - Zero-initialise the NOBITS sections. 9865f546a1SSandrine Bailleux * There are 2 of them: 9965f546a1SSandrine Bailleux * - the .bss section; 10065f546a1SSandrine Bailleux * - the coherent memory section. 10165f546a1SSandrine Bailleux * - Copy the data section from BL1 image 10265f546a1SSandrine Bailleux * (stored in ROM) to the correct location 10365f546a1SSandrine Bailleux * in RAM. 10465f546a1SSandrine Bailleux * --------------------------------------------- 10565f546a1SSandrine Bailleux */ 10665f546a1SSandrine Bailleux ldr x0, =__BSS_START__ 10765f546a1SSandrine Bailleux ldr x1, =__BSS_SIZE__ 10865f546a1SSandrine Bailleux bl zeromem16 10965f546a1SSandrine Bailleux 11065f546a1SSandrine Bailleux ldr x0, =__COHERENT_RAM_START__ 11165f546a1SSandrine Bailleux ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 11265f546a1SSandrine Bailleux bl zeromem16 11365f546a1SSandrine Bailleux 11465f546a1SSandrine Bailleux ldr x0, =__DATA_RAM_START__ 11565f546a1SSandrine Bailleux ldr x1, =__DATA_ROM_START__ 11665f546a1SSandrine Bailleux ldr x2, =__DATA_SIZE__ 11765f546a1SSandrine Bailleux bl memcpy16 11865f546a1SSandrine Bailleux 11965f546a1SSandrine Bailleux /* --------------------------------------------- 1204f6ad66aSAchin Gupta * Initialize platform and jump to our c-entry 1214f6ad66aSAchin Gupta * point for this type of reset 1224f6ad66aSAchin Gupta * --------------------------------------------- 1234f6ad66aSAchin Gupta */ 1244f6ad66aSAchin Gupta adr x0, bl1_main 1254f6ad66aSAchin Gupta bl platform_cold_boot_init 1264f6ad66aSAchin Gupta b _panic 1274f6ad66aSAchin Gupta 1284f6ad66aSAchin Gupta_do_warm_boot: 1294f6ad66aSAchin Gupta /* --------------------------------------------- 1304f6ad66aSAchin Gupta * Jump to BL31 for all warm boot init. 1314f6ad66aSAchin Gupta * --------------------------------------------- 1324f6ad66aSAchin Gupta */ 1334f6ad66aSAchin Gupta blr x0 1344f6ad66aSAchin Gupta_panic: 1354f6ad66aSAchin Gupta b _panic 136