1*4f6ad66aSAchin Gupta/* 2*4f6ad66aSAchin Gupta * Copyright (c) 2013, ARM Limited. All rights reserved. 3*4f6ad66aSAchin Gupta * 4*4f6ad66aSAchin Gupta * Redistribution and use in source and binary forms, with or without 5*4f6ad66aSAchin Gupta * modification, are permitted provided that the following conditions are met: 6*4f6ad66aSAchin Gupta * 7*4f6ad66aSAchin Gupta * Redistributions of source code must retain the above copyright notice, this 8*4f6ad66aSAchin Gupta * list of conditions and the following disclaimer. 9*4f6ad66aSAchin Gupta * 10*4f6ad66aSAchin Gupta * Redistributions in binary form must reproduce the above copyright notice, 11*4f6ad66aSAchin Gupta * this list of conditions and the following disclaimer in the documentation 12*4f6ad66aSAchin Gupta * and/or other materials provided with the distribution. 13*4f6ad66aSAchin Gupta * 14*4f6ad66aSAchin Gupta * Neither the name of ARM nor the names of its contributors may be used 15*4f6ad66aSAchin Gupta * to endorse or promote products derived from this software without specific 16*4f6ad66aSAchin Gupta * prior written permission. 17*4f6ad66aSAchin Gupta * 18*4f6ad66aSAchin Gupta * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*4f6ad66aSAchin Gupta * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*4f6ad66aSAchin Gupta * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*4f6ad66aSAchin Gupta * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*4f6ad66aSAchin Gupta * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*4f6ad66aSAchin Gupta * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*4f6ad66aSAchin Gupta * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*4f6ad66aSAchin Gupta * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*4f6ad66aSAchin Gupta * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*4f6ad66aSAchin Gupta * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*4f6ad66aSAchin Gupta * POSSIBILITY OF SUCH DAMAGE. 29*4f6ad66aSAchin Gupta */ 30*4f6ad66aSAchin Gupta 31*4f6ad66aSAchin Gupta 32*4f6ad66aSAchin Gupta .globl reset_handler 33*4f6ad66aSAchin Gupta 34*4f6ad66aSAchin Gupta 35*4f6ad66aSAchin Gupta .section reset_code, "ax"; .align 3 36*4f6ad66aSAchin Gupta 37*4f6ad66aSAchin Gupta /* ----------------------------------------------------- 38*4f6ad66aSAchin Gupta * reset_handler() is the entry point into the trusted 39*4f6ad66aSAchin Gupta * firmware code when a cpu is released from warm or 40*4f6ad66aSAchin Gupta * cold reset. 41*4f6ad66aSAchin Gupta * ----------------------------------------------------- 42*4f6ad66aSAchin Gupta */ 43*4f6ad66aSAchin Gupta 44*4f6ad66aSAchin Guptareset_handler:; .type reset_handler, %function 45*4f6ad66aSAchin Gupta /* --------------------------------------------- 46*4f6ad66aSAchin Gupta * Perform any processor specific actions upon 47*4f6ad66aSAchin Gupta * reset e.g. cache, tlb invalidations etc. 48*4f6ad66aSAchin Gupta * --------------------------------------------- 49*4f6ad66aSAchin Gupta */ 50*4f6ad66aSAchin Gupta bl cpu_reset_handler 51*4f6ad66aSAchin Gupta 52*4f6ad66aSAchin Gupta_wait_for_entrypoint: 53*4f6ad66aSAchin Gupta /* --------------------------------------------- 54*4f6ad66aSAchin Gupta * Find the type of reset and jump to handler 55*4f6ad66aSAchin Gupta * if present. If the handler is null then it is 56*4f6ad66aSAchin Gupta * a cold boot. The primary cpu will set up the 57*4f6ad66aSAchin Gupta * platform while the secondaries wait for 58*4f6ad66aSAchin Gupta * their turn to be woken up 59*4f6ad66aSAchin Gupta * --------------------------------------------- 60*4f6ad66aSAchin Gupta */ 61*4f6ad66aSAchin Gupta bl read_mpidr 62*4f6ad66aSAchin Gupta bl platform_get_entrypoint 63*4f6ad66aSAchin Gupta cbnz x0, _do_warm_boot 64*4f6ad66aSAchin Gupta bl read_mpidr 65*4f6ad66aSAchin Gupta bl platform_is_primary_cpu 66*4f6ad66aSAchin Gupta cbnz x0, _do_cold_boot 67*4f6ad66aSAchin Gupta 68*4f6ad66aSAchin Gupta /* --------------------------------------------- 69*4f6ad66aSAchin Gupta * Perform any platform specific secondary cpu 70*4f6ad66aSAchin Gupta * actions 71*4f6ad66aSAchin Gupta * --------------------------------------------- 72*4f6ad66aSAchin Gupta */ 73*4f6ad66aSAchin Gupta bl plat_secondary_cold_boot_setup 74*4f6ad66aSAchin Gupta b _wait_for_entrypoint 75*4f6ad66aSAchin Gupta 76*4f6ad66aSAchin Gupta_do_cold_boot: 77*4f6ad66aSAchin Gupta /* --------------------------------------------- 78*4f6ad66aSAchin Gupta * Initialize platform and jump to our c-entry 79*4f6ad66aSAchin Gupta * point for this type of reset 80*4f6ad66aSAchin Gupta * --------------------------------------------- 81*4f6ad66aSAchin Gupta */ 82*4f6ad66aSAchin Gupta adr x0, bl1_main 83*4f6ad66aSAchin Gupta bl platform_cold_boot_init 84*4f6ad66aSAchin Gupta b _panic 85*4f6ad66aSAchin Gupta 86*4f6ad66aSAchin Gupta_do_warm_boot: 87*4f6ad66aSAchin Gupta /* --------------------------------------------- 88*4f6ad66aSAchin Gupta * Jump to BL31 for all warm boot init. 89*4f6ad66aSAchin Gupta * --------------------------------------------- 90*4f6ad66aSAchin Gupta */ 91*4f6ad66aSAchin Gupta blr x0 92*4f6ad66aSAchin Gupta_panic: 93*4f6ad66aSAchin Gupta b _panic 94