14f6ad66aSAchin Gupta/* 2*18f2efd6SDavid Cunado * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 34f6ad66aSAchin Gupta * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 54f6ad66aSAchin Gupta */ 64f6ad66aSAchin Gupta 7c10bd2ceSSandrine Bailleux#include <arch.h> 852010cc7SSandrine Bailleux#include <el3_common_macros.S> 94f6ad66aSAchin Gupta 109f98aa1aSJeenu Viswambharan .globl bl1_entrypoint 114f6ad66aSAchin Gupta 124f6ad66aSAchin Gupta 134f6ad66aSAchin Gupta /* ----------------------------------------------------- 149f98aa1aSJeenu Viswambharan * bl1_entrypoint() is the entry point into the trusted 154f6ad66aSAchin Gupta * firmware code when a cpu is released from warm or 164f6ad66aSAchin Gupta * cold reset. 174f6ad66aSAchin Gupta * ----------------------------------------------------- 184f6ad66aSAchin Gupta */ 194f6ad66aSAchin Gupta 200a30cf54SAndrew Thoelkefunc bl1_entrypoint 21bf031bbaSSandrine Bailleux /* --------------------------------------------------------------------- 22bf031bbaSSandrine Bailleux * If the reset address is programmable then bl1_entrypoint() is 23bf031bbaSSandrine Bailleux * executed only on the cold boot path. Therefore, we can skip the warm 24bf031bbaSSandrine Bailleux * boot mailbox mechanism. 25bf031bbaSSandrine Bailleux * --------------------------------------------------------------------- 26bf031bbaSSandrine Bailleux */ 2752010cc7SSandrine Bailleux el3_entrypoint_common \ 28*18f2efd6SDavid Cunado _init_sctlr=1 \ 29bf031bbaSSandrine Bailleux _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 30a9bec67dSSandrine Bailleux _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 3152010cc7SSandrine Bailleux _init_memory=1 \ 3252010cc7SSandrine Bailleux _init_c_runtime=1 \ 3352010cc7SSandrine Bailleux _exception_vectors=bl1_exceptions 344f6ad66aSAchin Gupta 354f6ad66aSAchin Gupta /* --------------------------------------------- 36dbad1bacSVikram Kanigiri * Architectural init. can be generic e.g. 37dbad1bacSVikram Kanigiri * enabling stack alignment and platform spec- 38dbad1bacSVikram Kanigiri * ific e.g. MMU & page table setup as per the 39dbad1bacSVikram Kanigiri * platform memory map. Perform the latter here 40dbad1bacSVikram Kanigiri * and the former in bl1_main. 414f6ad66aSAchin Gupta * --------------------------------------------- 424f6ad66aSAchin Gupta */ 43dbad1bacSVikram Kanigiri bl bl1_early_platform_setup 44dbad1bacSVikram Kanigiri bl bl1_plat_arch_setup 45dbad1bacSVikram Kanigiri 46dbad1bacSVikram Kanigiri /* -------------------------------------------------- 47dbad1bacSVikram Kanigiri * Initialize platform and jump to our c-entry point 487baff11fSYatharth Kochar * for this type of reset. 49dbad1bacSVikram Kanigiri * -------------------------------------------------- 50dbad1bacSVikram Kanigiri */ 51dbad1bacSVikram Kanigiri bl bl1_main 527baff11fSYatharth Kochar 537baff11fSYatharth Kochar /* -------------------------------------------------- 547baff11fSYatharth Kochar * Do the transition to next boot image. 557baff11fSYatharth Kochar * -------------------------------------------------- 567baff11fSYatharth Kochar */ 577baff11fSYatharth Kochar b el3_exit 588b779620SKévin Petitendfunc bl1_entrypoint 59