1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <context.h> 34 #include <context_mgmt.h> 35 #include <debug.h> 36 #include <platform.h> 37 38 /* 39 * Following array will be used for context management. 40 * There are 2 instances, for the Secure and Non-Secure contexts. 41 */ 42 static cpu_context_t bl1_cpu_context[2]; 43 44 /* Following contains the cpu context pointers. */ 45 static void *bl1_cpu_context_ptr[2]; 46 47 48 void *cm_get_context(uint32_t security_state) 49 { 50 assert(sec_state_is_valid(security_state)); 51 return bl1_cpu_context_ptr[security_state]; 52 } 53 54 void cm_set_context(void *context, uint32_t security_state) 55 { 56 assert(sec_state_is_valid(security_state)); 57 bl1_cpu_context_ptr[security_state] = context; 58 } 59 60 /******************************************************************************* 61 * This function prepares the context for Secure/Normal world images. 62 * Normal world images are transitioned to EL2(if supported) else EL1. 63 ******************************************************************************/ 64 void bl1_prepare_next_image(unsigned int image_id) 65 { 66 unsigned int security_state; 67 image_desc_t *image_desc; 68 entry_point_info_t *next_bl_ep; 69 70 #if CTX_INCLUDE_AARCH32_REGS 71 /* 72 * Ensure that the build flag to save AArch32 system registers in CPU 73 * context is not set for AArch64-only platforms. 74 */ 75 if (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL1_SHIFT) 76 & ID_AA64PFR0_ELX_MASK) == 0x1) { 77 ERROR("EL1 supports AArch64-only. Please set build flag " 78 "CTX_INCLUDE_AARCH32_REGS = 0"); 79 panic(); 80 } 81 #endif 82 83 /* Get the image descriptor. */ 84 image_desc = bl1_plat_get_image_desc(image_id); 85 assert(image_desc); 86 87 /* Get the entry point info. */ 88 next_bl_ep = &image_desc->ep_info; 89 90 /* Get the image security state. */ 91 security_state = GET_SECURITY_STATE(next_bl_ep->h.attr); 92 93 /* Setup the Secure/Non-Secure context if not done already. */ 94 if (!cm_get_context(security_state)) 95 cm_set_context(&bl1_cpu_context[security_state], security_state); 96 97 /* Prepare the SPSR for the next BL image. */ 98 if (security_state == SECURE) { 99 next_bl_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 100 DISABLE_ALL_EXCEPTIONS); 101 } else { 102 /* Use EL2 if supported else use EL1. */ 103 if (read_id_aa64pfr0_el1() & 104 (ID_AA64PFR0_ELX_MASK << ID_AA64PFR0_EL2_SHIFT)) { 105 next_bl_ep->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 106 DISABLE_ALL_EXCEPTIONS); 107 } else { 108 next_bl_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 109 DISABLE_ALL_EXCEPTIONS); 110 } 111 } 112 113 /* Allow platform to make change */ 114 bl1_plat_set_ep_info(image_id, next_bl_ep); 115 116 /* Prepare the context for the next BL image. */ 117 cm_init_my_context(next_bl_ep); 118 cm_prepare_el3_exit(security_state); 119 120 /* Indicate that image is in execution state. */ 121 image_desc->state = IMAGE_STATE_EXECUTED; 122 123 print_entry_point_info(next_bl_ep); 124 } 125