1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 34 /******************************************************************************* 35 * Function that does the first bit of architectural setup that affects 36 * execution in the non-secure address space. 37 ******************************************************************************/ 38 void bl1_arch_setup(void) 39 { 40 unsigned long tmp_reg = 0; 41 42 /* Enable alignment checks and set the exception endianess to LE */ 43 tmp_reg = read_sctlr_el3(); 44 tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT); 45 tmp_reg &= ~SCTLR_EE_BIT; 46 write_sctlr_el3(tmp_reg); 47 48 /* 49 * Enable HVCs, route FIQs to EL3, set the next EL to be AArch64, route 50 * external abort and SError interrupts to EL3 51 */ 52 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_EA_BIT | 53 SCR_FIQ_BIT; 54 write_scr(tmp_reg); 55 56 /* 57 * Enable SError and Debug exceptions 58 */ 59 enable_serror(); 60 enable_debug_exceptions(); 61 } 62 63 /******************************************************************************* 64 * Set the Secure EL1 required architectural state 65 ******************************************************************************/ 66 void bl1_arch_next_el_setup(void) { 67 unsigned long next_sctlr; 68 69 /* Use the same endianness than the current BL */ 70 next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT); 71 72 /* Set SCTLR Secure EL1 */ 73 next_sctlr |= SCTLR_EL1_RES1; 74 75 write_sctlr_el1(next_sctlr); 76 } 77