xref: /rk3399_ARM-atf/bl1/aarch64/bl1_arch_setup.c (revision 82cb2c1ad9897473743f08437d0a3995bed561b9)
14f6ad66aSAchin Gupta /*
2e83b0cadSDan Handley  * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
34f6ad66aSAchin Gupta  *
4*82cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
54f6ad66aSAchin Gupta  */
64f6ad66aSAchin Gupta 
797043ac9SDan Handley #include <arch.h>
84f6ad66aSAchin Gupta #include <arch_helpers.h>
94f6ad66aSAchin Gupta 
104f6ad66aSAchin Gupta /*******************************************************************************
114f6ad66aSAchin Gupta  * Function that does the first bit of architectural setup that affects
124f6ad66aSAchin Gupta  * execution in the non-secure address space.
134f6ad66aSAchin Gupta  ******************************************************************************/
144f6ad66aSAchin Gupta void bl1_arch_setup(void)
154f6ad66aSAchin Gupta {
160c8d4fefSAchin Gupta 	/* Set the next EL to be AArch64 */
17adb4fcfbSGerald Lejeune 	write_scr_el3(read_scr_el3() | SCR_RW_BIT);
184f6ad66aSAchin Gupta }
194f6ad66aSAchin Gupta 
204f6ad66aSAchin Gupta /*******************************************************************************
214f6ad66aSAchin Gupta  * Set the Secure EL1 required architectural state
224f6ad66aSAchin Gupta  ******************************************************************************/
234f2104ffSJuan Castillo void bl1_arch_next_el_setup(void)
244f2104ffSJuan Castillo {
256ba0b6d6SVikram Kanigiri 	unsigned long next_sctlr;
264f6ad66aSAchin Gupta 
274f6ad66aSAchin Gupta 	/* Use the same endianness than the current BL */
286ba0b6d6SVikram Kanigiri 	next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT);
294f6ad66aSAchin Gupta 
304f6ad66aSAchin Gupta 	/* Set SCTLR Secure EL1 */
314f6ad66aSAchin Gupta 	next_sctlr |= SCTLR_EL1_RES1;
324f6ad66aSAchin Gupta 
334f6ad66aSAchin Gupta 	write_sctlr_el1(next_sctlr);
344f6ad66aSAchin Gupta }
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