1*4f6ad66aSAchin Gupta /* 2*4f6ad66aSAchin Gupta * Copyright (c) 2013, ARM Limited. All rights reserved. 3*4f6ad66aSAchin Gupta * 4*4f6ad66aSAchin Gupta * Redistribution and use in source and binary forms, with or without 5*4f6ad66aSAchin Gupta * modification, are permitted provided that the following conditions are met: 6*4f6ad66aSAchin Gupta * 7*4f6ad66aSAchin Gupta * Redistributions of source code must retain the above copyright notice, this 8*4f6ad66aSAchin Gupta * list of conditions and the following disclaimer. 9*4f6ad66aSAchin Gupta * 10*4f6ad66aSAchin Gupta * Redistributions in binary form must reproduce the above copyright notice, 11*4f6ad66aSAchin Gupta * this list of conditions and the following disclaimer in the documentation 12*4f6ad66aSAchin Gupta * and/or other materials provided with the distribution. 13*4f6ad66aSAchin Gupta * 14*4f6ad66aSAchin Gupta * Neither the name of ARM nor the names of its contributors may be used 15*4f6ad66aSAchin Gupta * to endorse or promote products derived from this software without specific 16*4f6ad66aSAchin Gupta * prior written permission. 17*4f6ad66aSAchin Gupta * 18*4f6ad66aSAchin Gupta * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*4f6ad66aSAchin Gupta * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*4f6ad66aSAchin Gupta * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*4f6ad66aSAchin Gupta * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*4f6ad66aSAchin Gupta * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*4f6ad66aSAchin Gupta * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*4f6ad66aSAchin Gupta * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*4f6ad66aSAchin Gupta * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*4f6ad66aSAchin Gupta * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*4f6ad66aSAchin Gupta * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*4f6ad66aSAchin Gupta * POSSIBILITY OF SUCH DAMAGE. 29*4f6ad66aSAchin Gupta */ 30*4f6ad66aSAchin Gupta 31*4f6ad66aSAchin Gupta #include <arch_helpers.h> 32*4f6ad66aSAchin Gupta #include <platform.h> 33*4f6ad66aSAchin Gupta #include <assert.h> 34*4f6ad66aSAchin Gupta 35*4f6ad66aSAchin Gupta /******************************************************************************* 36*4f6ad66aSAchin Gupta * Function that does the first bit of architectural setup that affects 37*4f6ad66aSAchin Gupta * execution in the non-secure address space. 38*4f6ad66aSAchin Gupta ******************************************************************************/ 39*4f6ad66aSAchin Gupta void bl1_arch_setup(void) 40*4f6ad66aSAchin Gupta { 41*4f6ad66aSAchin Gupta unsigned long tmp_reg = 0; 42*4f6ad66aSAchin Gupta unsigned int counter_base_frequency; 43*4f6ad66aSAchin Gupta 44*4f6ad66aSAchin Gupta /* Enable alignment checks and set the exception endianess to LE */ 45*4f6ad66aSAchin Gupta tmp_reg = read_sctlr(); 46*4f6ad66aSAchin Gupta tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT); 47*4f6ad66aSAchin Gupta tmp_reg &= ~SCTLR_EE_BIT; 48*4f6ad66aSAchin Gupta write_sctlr(tmp_reg); 49*4f6ad66aSAchin Gupta 50*4f6ad66aSAchin Gupta /* 51*4f6ad66aSAchin Gupta * Enable HVCs, route FIQs to EL3, set the next EL to be aarch64 52*4f6ad66aSAchin Gupta */ 53*4f6ad66aSAchin Gupta tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_FIQ_BIT; 54*4f6ad66aSAchin Gupta write_scr(tmp_reg); 55*4f6ad66aSAchin Gupta 56*4f6ad66aSAchin Gupta /* Do not trap coprocessor accesses from lower ELs to EL3 */ 57*4f6ad66aSAchin Gupta write_cptr_el3(0); 58*4f6ad66aSAchin Gupta 59*4f6ad66aSAchin Gupta /* Read the frequency from Frequency modes table */ 60*4f6ad66aSAchin Gupta counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF); 61*4f6ad66aSAchin Gupta /* The first entry of the frequency modes table must not be 0 */ 62*4f6ad66aSAchin Gupta assert(counter_base_frequency != 0); 63*4f6ad66aSAchin Gupta 64*4f6ad66aSAchin Gupta /* Program the counter frequency */ 65*4f6ad66aSAchin Gupta write_cntfrq_el0(counter_base_frequency); 66*4f6ad66aSAchin Gupta return; 67*4f6ad66aSAchin Gupta } 68*4f6ad66aSAchin Gupta 69*4f6ad66aSAchin Gupta /******************************************************************************* 70*4f6ad66aSAchin Gupta * Set the Secure EL1 required architectural state 71*4f6ad66aSAchin Gupta ******************************************************************************/ 72*4f6ad66aSAchin Gupta void bl1_arch_next_el_setup(void) { 73*4f6ad66aSAchin Gupta unsigned long current_sctlr, next_sctlr; 74*4f6ad66aSAchin Gupta 75*4f6ad66aSAchin Gupta /* Use the same endianness than the current BL */ 76*4f6ad66aSAchin Gupta current_sctlr = read_sctlr(); 77*4f6ad66aSAchin Gupta next_sctlr = (current_sctlr & SCTLR_EE_BIT); 78*4f6ad66aSAchin Gupta 79*4f6ad66aSAchin Gupta /* Set SCTLR Secure EL1 */ 80*4f6ad66aSAchin Gupta next_sctlr |= SCTLR_EL1_RES1; 81*4f6ad66aSAchin Gupta 82*4f6ad66aSAchin Gupta write_sctlr_el1(next_sctlr); 83*4f6ad66aSAchin Gupta } 84