1*f3b4914bSYatharth Kochar/* 2*f3b4914bSYatharth Kochar * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*f3b4914bSYatharth Kochar * 4*f3b4914bSYatharth Kochar * Redistribution and use in source and binary forms, with or without 5*f3b4914bSYatharth Kochar * modification, are permitted provided that the following conditions are met: 6*f3b4914bSYatharth Kochar * 7*f3b4914bSYatharth Kochar * Redistributions of source code must retain the above copyright notice, this 8*f3b4914bSYatharth Kochar * list of conditions and the following disclaimer. 9*f3b4914bSYatharth Kochar * 10*f3b4914bSYatharth Kochar * Redistributions in binary form must reproduce the above copyright notice, 11*f3b4914bSYatharth Kochar * this list of conditions and the following disclaimer in the documentation 12*f3b4914bSYatharth Kochar * and/or other materials provided with the distribution. 13*f3b4914bSYatharth Kochar * 14*f3b4914bSYatharth Kochar * Neither the name of ARM nor the names of its contributors may be used 15*f3b4914bSYatharth Kochar * to endorse or promote products derived from this software without specific 16*f3b4914bSYatharth Kochar * prior written permission. 17*f3b4914bSYatharth Kochar * 18*f3b4914bSYatharth Kochar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*f3b4914bSYatharth Kochar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*f3b4914bSYatharth Kochar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*f3b4914bSYatharth Kochar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*f3b4914bSYatharth Kochar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*f3b4914bSYatharth Kochar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*f3b4914bSYatharth Kochar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*f3b4914bSYatharth Kochar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*f3b4914bSYatharth Kochar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*f3b4914bSYatharth Kochar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*f3b4914bSYatharth Kochar * POSSIBILITY OF SUCH DAMAGE. 29*f3b4914bSYatharth Kochar */ 30*f3b4914bSYatharth Kochar 31*f3b4914bSYatharth Kochar#include <arch.h> 32*f3b4914bSYatharth Kochar#include <asm_macros.S> 33*f3b4914bSYatharth Kochar#include <bl1.h> 34*f3b4914bSYatharth Kochar#include <bl_common.h> 35*f3b4914bSYatharth Kochar 36*f3b4914bSYatharth Kochar .globl bl1_aarch32_smc_handler 37*f3b4914bSYatharth Kochar 38*f3b4914bSYatharth Kochar 39*f3b4914bSYatharth Kocharfunc bl1_aarch32_smc_handler 40*f3b4914bSYatharth Kochar /* ------------------------------------------------ 41*f3b4914bSYatharth Kochar * SMC in BL1 is handled assuming that the MMU is 42*f3b4914bSYatharth Kochar * turned off by BL2. 43*f3b4914bSYatharth Kochar * ------------------------------------------------ 44*f3b4914bSYatharth Kochar */ 45*f3b4914bSYatharth Kochar 46*f3b4914bSYatharth Kochar /* ---------------------------------------------- 47*f3b4914bSYatharth Kochar * Only RUN_IMAGE SMC is supported. 48*f3b4914bSYatharth Kochar * ---------------------------------------------- 49*f3b4914bSYatharth Kochar */ 50*f3b4914bSYatharth Kochar mov r8, #BL1_SMC_RUN_IMAGE 51*f3b4914bSYatharth Kochar cmp r8, r0 52*f3b4914bSYatharth Kochar blne report_exception 53*f3b4914bSYatharth Kochar 54*f3b4914bSYatharth Kochar /* ------------------------------------------------ 55*f3b4914bSYatharth Kochar * Make sure only Secure world reaches here. 56*f3b4914bSYatharth Kochar * ------------------------------------------------ 57*f3b4914bSYatharth Kochar */ 58*f3b4914bSYatharth Kochar ldcopr r8, SCR 59*f3b4914bSYatharth Kochar tst r8, #SCR_NS_BIT 60*f3b4914bSYatharth Kochar blne report_exception 61*f3b4914bSYatharth Kochar 62*f3b4914bSYatharth Kochar /* --------------------------------------------------------------------- 63*f3b4914bSYatharth Kochar * Pass control to next secure image. 64*f3b4914bSYatharth Kochar * Here it expects r1 to contain the address of a entry_point_info_t 65*f3b4914bSYatharth Kochar * structure describing the BL entrypoint. 66*f3b4914bSYatharth Kochar * --------------------------------------------------------------------- 67*f3b4914bSYatharth Kochar */ 68*f3b4914bSYatharth Kochar mov r8, r1 69*f3b4914bSYatharth Kochar mov r0, r1 70*f3b4914bSYatharth Kochar bl bl1_print_next_bl_ep_info 71*f3b4914bSYatharth Kochar 72*f3b4914bSYatharth Kochar#if SPIN_ON_BL1_EXIT 73*f3b4914bSYatharth Kochar bl print_debug_loop_message 74*f3b4914bSYatharth Kochardebug_loop: 75*f3b4914bSYatharth Kochar b debug_loop 76*f3b4914bSYatharth Kochar#endif 77*f3b4914bSYatharth Kochar 78*f3b4914bSYatharth Kochar mov r0, r8 79*f3b4914bSYatharth Kochar bl bl1_plat_prepare_exit 80*f3b4914bSYatharth Kochar 81*f3b4914bSYatharth Kochar stcopr r0, TLBIALL 82*f3b4914bSYatharth Kochar dsb sy 83*f3b4914bSYatharth Kochar isb 84*f3b4914bSYatharth Kochar 85*f3b4914bSYatharth Kochar /* 86*f3b4914bSYatharth Kochar * Extract PC and SPSR based on struct `entry_point_info_t` 87*f3b4914bSYatharth Kochar * and load it in LR and SPSR registers respectively. 88*f3b4914bSYatharth Kochar */ 89*f3b4914bSYatharth Kochar ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET] 90*f3b4914bSYatharth Kochar ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] 91*f3b4914bSYatharth Kochar msr spsr, r1 92*f3b4914bSYatharth Kochar 93*f3b4914bSYatharth Kochar add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET 94*f3b4914bSYatharth Kochar ldm r8, {r0, r1, r2, r3} 95*f3b4914bSYatharth Kochar eret 96*f3b4914bSYatharth Kocharendfunc bl1_aarch32_smc_handler 97