1f3b4914bSYatharth Kochar/* 2f3b4914bSYatharth Kochar * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3f3b4914bSYatharth Kochar * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5f3b4914bSYatharth Kochar */ 6f3b4914bSYatharth Kochar 7f3b4914bSYatharth Kochar#include <arch.h> 8f3b4914bSYatharth Kochar#include <asm_macros.S> 9f3b4914bSYatharth Kochar#include <bl1.h> 10f3b4914bSYatharth Kochar#include <bl_common.h> 11f3b4914bSYatharth Kochar 12f3b4914bSYatharth Kochar .globl bl1_aarch32_smc_handler 13f3b4914bSYatharth Kochar 14f3b4914bSYatharth Kochar 15f3b4914bSYatharth Kocharfunc bl1_aarch32_smc_handler 16f3b4914bSYatharth Kochar /* ------------------------------------------------ 17f3b4914bSYatharth Kochar * SMC in BL1 is handled assuming that the MMU is 18f3b4914bSYatharth Kochar * turned off by BL2. 19f3b4914bSYatharth Kochar * ------------------------------------------------ 20f3b4914bSYatharth Kochar */ 21f3b4914bSYatharth Kochar 22f3b4914bSYatharth Kochar /* ---------------------------------------------- 23f3b4914bSYatharth Kochar * Only RUN_IMAGE SMC is supported. 24f3b4914bSYatharth Kochar * ---------------------------------------------- 25f3b4914bSYatharth Kochar */ 26f3b4914bSYatharth Kochar mov r8, #BL1_SMC_RUN_IMAGE 27f3b4914bSYatharth Kochar cmp r8, r0 28f3b4914bSYatharth Kochar blne report_exception 29f3b4914bSYatharth Kochar 30f3b4914bSYatharth Kochar /* ------------------------------------------------ 31f3b4914bSYatharth Kochar * Make sure only Secure world reaches here. 32f3b4914bSYatharth Kochar * ------------------------------------------------ 33f3b4914bSYatharth Kochar */ 34f3b4914bSYatharth Kochar ldcopr r8, SCR 35f3b4914bSYatharth Kochar tst r8, #SCR_NS_BIT 36f3b4914bSYatharth Kochar blne report_exception 37f3b4914bSYatharth Kochar 38f3b4914bSYatharth Kochar /* --------------------------------------------------------------------- 39f3b4914bSYatharth Kochar * Pass control to next secure image. 40f3b4914bSYatharth Kochar * Here it expects r1 to contain the address of a entry_point_info_t 41f3b4914bSYatharth Kochar * structure describing the BL entrypoint. 42f3b4914bSYatharth Kochar * --------------------------------------------------------------------- 43f3b4914bSYatharth Kochar */ 44f3b4914bSYatharth Kochar mov r8, r1 45f3b4914bSYatharth Kochar mov r0, r1 46f3b4914bSYatharth Kochar bl bl1_print_next_bl_ep_info 47f3b4914bSYatharth Kochar 48f3b4914bSYatharth Kochar#if SPIN_ON_BL1_EXIT 49f3b4914bSYatharth Kochar bl print_debug_loop_message 50f3b4914bSYatharth Kochardebug_loop: 51f3b4914bSYatharth Kochar b debug_loop 52f3b4914bSYatharth Kochar#endif 53f3b4914bSYatharth Kochar 54f3b4914bSYatharth Kochar mov r0, r8 55f3b4914bSYatharth Kochar bl bl1_plat_prepare_exit 56f3b4914bSYatharth Kochar 57f3b4914bSYatharth Kochar stcopr r0, TLBIALL 58f3b4914bSYatharth Kochar dsb sy 59f3b4914bSYatharth Kochar isb 60f3b4914bSYatharth Kochar 61f3b4914bSYatharth Kochar /* 62f3b4914bSYatharth Kochar * Extract PC and SPSR based on struct `entry_point_info_t` 63f3b4914bSYatharth Kochar * and load it in LR and SPSR registers respectively. 64f3b4914bSYatharth Kochar */ 65f3b4914bSYatharth Kochar ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET] 66f3b4914bSYatharth Kochar ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] 67f3b4914bSYatharth Kochar msr spsr, r1 68f3b4914bSYatharth Kochar 69f3b4914bSYatharth Kochar add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET 70f3b4914bSYatharth Kochar ldm r8, {r0, r1, r2, r3} 71f3b4914bSYatharth Kochar eret 72f3b4914bSYatharth Kocharendfunc bl1_aarch32_smc_handler 73