1/* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <context.h> 11#include <el3_common_macros.S> 12#include <smccc_helpers.h> 13#include <smccc_macros.S> 14 15 .globl bl1_vector_table 16 .globl bl1_entrypoint 17 18 /* ----------------------------------------------------- 19 * Setup the vector table to support SVC & MON mode. 20 * ----------------------------------------------------- 21 */ 22vector_base bl1_vector_table 23 b bl1_entrypoint 24 b report_exception /* Undef */ 25 b bl1_aarch32_smc_handler /* SMC call */ 26 b report_exception /* Prefetch abort */ 27 b report_exception /* Data abort */ 28 b report_exception /* Reserved */ 29 b report_exception /* IRQ */ 30 b report_exception /* FIQ */ 31 32 /* ----------------------------------------------------- 33 * bl1_entrypoint() is the entry point into the trusted 34 * firmware code when a cpu is released from warm or 35 * cold reset. 36 * ----------------------------------------------------- 37 */ 38 39func bl1_entrypoint 40/* --------------------------------------------------------------------- 41* If the reset address is programmable then bl1_entrypoint() is 42* executed only on the cold boot path. Therefore, we can skip the warm 43* boot mailbox mechanism. 44* --------------------------------------------------------------------- 45*/ 46 el3_entrypoint_common \ 47 _init_sctlr=1 \ 48 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 49 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 50 _init_memory=1 \ 51 _init_c_runtime=1 \ 52 _exception_vectors=bl1_vector_table 53 54 /* ----------------------------------------------------- 55 * Perform BL1 setup 56 * ----------------------------------------------------- 57 */ 58 bl bl1_setup 59 60 /* ----------------------------------------------------- 61 * Jump to main function. 62 * ----------------------------------------------------- 63 */ 64 bl bl1_main 65 66 /* ----------------------------------------------------- 67 * Jump to next image. 68 * ----------------------------------------------------- 69 */ 70 71 /* 72 * Get the smc_context for next BL image, 73 * program the gp/system registers and save it in `r4`. 74 */ 75 bl smc_get_next_ctx 76 mov r4, r0 77 78 /* Only turn-off MMU if going to secure world */ 79 ldr r5, [r4, #SMC_CTX_SCR] 80 tst r5, #SCR_NS_BIT 81 bne skip_mmu_off 82 83 /* 84 * MMU needs to be disabled because both BL1 and BL2/BL2U execute 85 * in PL1, and therefore share the same address space. 86 * BL2/BL2U will initialize the address space according to its 87 * own requirement. 88 */ 89 bl disable_mmu_icache_secure 90 stcopr r0, TLBIALL 91 dsb sy 92 isb 93 94skip_mmu_off: 95 /* Restore smc_context from `r4` and exit secure monitor mode. */ 96 mov r0, r4 97 monitor_exit 98endfunc bl1_entrypoint 99