1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <bl_common.h> 34#include <context.h> 35#include <el3_common_macros.S> 36#include <smcc_helpers.h> 37#include <smcc_macros.S> 38 39 .globl bl1_vector_table 40 .globl bl1_entrypoint 41 42 /* ----------------------------------------------------- 43 * Setup the vector table to support SVC & MON mode. 44 * ----------------------------------------------------- 45 */ 46vector_base bl1_vector_table 47 b bl1_entrypoint 48 b report_exception /* Undef */ 49 b bl1_aarch32_smc_handler /* SMC call */ 50 b report_exception /* Prefetch abort */ 51 b report_exception /* Data abort */ 52 b report_exception /* Reserved */ 53 b report_exception /* IRQ */ 54 b report_exception /* FIQ */ 55 56 /* ----------------------------------------------------- 57 * bl1_entrypoint() is the entry point into the trusted 58 * firmware code when a cpu is released from warm or 59 * cold reset. 60 * ----------------------------------------------------- 61 */ 62 63func bl1_entrypoint 64/* --------------------------------------------------------------------- 65* If the reset address is programmable then bl1_entrypoint() is 66* executed only on the cold boot path. Therefore, we can skip the warm 67* boot mailbox mechanism. 68* --------------------------------------------------------------------- 69*/ 70 el3_entrypoint_common \ 71 _set_endian=1 \ 72 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 73 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 74 _init_memory=1 \ 75 _init_c_runtime=1 \ 76 _exception_vectors=bl1_vector_table 77 78 /* ----------------------------------------------------- 79 * Perform early platform setup & platform 80 * specific early arch. setup e.g. mmu setup 81 * ----------------------------------------------------- 82 */ 83 bl bl1_early_platform_setup 84 bl bl1_plat_arch_setup 85 86 /* ----------------------------------------------------- 87 * Jump to main function. 88 * ----------------------------------------------------- 89 */ 90 bl bl1_main 91 92 /* ----------------------------------------------------- 93 * Jump to next image. 94 * ----------------------------------------------------- 95 */ 96 97 /* 98 * MMU needs to be disabled because both BL1 and BL2 execute 99 * in PL1, and therefore share the same address space. 100 * BL2 will initialize the address space according to its 101 * own requirement. 102 */ 103 bl disable_mmu_icache_secure 104 stcopr r0, TLBIALL 105 dsb sy 106 isb 107 108 /* Get the cpu_context for next BL image */ 109 bl cm_get_next_context 110 111 /* Restore the SCR */ 112 ldr r2, [r0, #CTX_REGS_OFFSET + CTX_SCR] 113 stcopr r2, SCR 114 isb 115 116 /* 117 * Get the smc_context for next BL image, 118 * program the gp/system registers and exit 119 * secure monitor mode 120 */ 121 bl smc_get_next_ctx 122 smcc_restore_gp_mode_regs 123 eret 124endfunc bl1_entrypoint 125