1f3b4914bSYatharth Kochar/* 2f3b4914bSYatharth Kochar * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3f3b4914bSYatharth Kochar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5f3b4914bSYatharth Kochar */ 6f3b4914bSYatharth Kochar 7f3b4914bSYatharth Kochar#include <arch.h> 8f3b4914bSYatharth Kochar#include <asm_macros.S> 9f3b4914bSYatharth Kochar#include <bl_common.h> 10f3b4914bSYatharth Kochar#include <context.h> 11f3b4914bSYatharth Kochar#include <el3_common_macros.S> 12f3b4914bSYatharth Kochar#include <smcc_helpers.h> 13f3b4914bSYatharth Kochar#include <smcc_macros.S> 14f3b4914bSYatharth Kochar 15f3b4914bSYatharth Kochar .globl bl1_vector_table 16f3b4914bSYatharth Kochar .globl bl1_entrypoint 17f3b4914bSYatharth Kochar 18f3b4914bSYatharth Kochar /* ----------------------------------------------------- 19f3b4914bSYatharth Kochar * Setup the vector table to support SVC & MON mode. 20f3b4914bSYatharth Kochar * ----------------------------------------------------- 21f3b4914bSYatharth Kochar */ 22f3b4914bSYatharth Kocharvector_base bl1_vector_table 23f3b4914bSYatharth Kochar b bl1_entrypoint 24f3b4914bSYatharth Kochar b report_exception /* Undef */ 25f3b4914bSYatharth Kochar b bl1_aarch32_smc_handler /* SMC call */ 26f3b4914bSYatharth Kochar b report_exception /* Prefetch abort */ 27f3b4914bSYatharth Kochar b report_exception /* Data abort */ 28f3b4914bSYatharth Kochar b report_exception /* Reserved */ 29f3b4914bSYatharth Kochar b report_exception /* IRQ */ 30f3b4914bSYatharth Kochar b report_exception /* FIQ */ 31f3b4914bSYatharth Kochar 32f3b4914bSYatharth Kochar /* ----------------------------------------------------- 33f3b4914bSYatharth Kochar * bl1_entrypoint() is the entry point into the trusted 34f3b4914bSYatharth Kochar * firmware code when a cpu is released from warm or 35f3b4914bSYatharth Kochar * cold reset. 36f3b4914bSYatharth Kochar * ----------------------------------------------------- 37f3b4914bSYatharth Kochar */ 38f3b4914bSYatharth Kochar 39f3b4914bSYatharth Kocharfunc bl1_entrypoint 40f3b4914bSYatharth Kochar/* --------------------------------------------------------------------- 41f3b4914bSYatharth Kochar* If the reset address is programmable then bl1_entrypoint() is 42f3b4914bSYatharth Kochar* executed only on the cold boot path. Therefore, we can skip the warm 43f3b4914bSYatharth Kochar* boot mailbox mechanism. 44f3b4914bSYatharth Kochar* --------------------------------------------------------------------- 45f3b4914bSYatharth Kochar*/ 46f3b4914bSYatharth Kochar el3_entrypoint_common \ 47f3b4914bSYatharth Kochar _set_endian=1 \ 48f3b4914bSYatharth Kochar _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 49f3b4914bSYatharth Kochar _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 50f3b4914bSYatharth Kochar _init_memory=1 \ 51f3b4914bSYatharth Kochar _init_c_runtime=1 \ 52f3b4914bSYatharth Kochar _exception_vectors=bl1_vector_table 53f3b4914bSYatharth Kochar 54f3b4914bSYatharth Kochar /* ----------------------------------------------------- 55f3b4914bSYatharth Kochar * Perform early platform setup & platform 56f3b4914bSYatharth Kochar * specific early arch. setup e.g. mmu setup 57f3b4914bSYatharth Kochar * ----------------------------------------------------- 58f3b4914bSYatharth Kochar */ 59f3b4914bSYatharth Kochar bl bl1_early_platform_setup 60f3b4914bSYatharth Kochar bl bl1_plat_arch_setup 61f3b4914bSYatharth Kochar 62f3b4914bSYatharth Kochar /* ----------------------------------------------------- 63f3b4914bSYatharth Kochar * Jump to main function. 64f3b4914bSYatharth Kochar * ----------------------------------------------------- 65f3b4914bSYatharth Kochar */ 66f3b4914bSYatharth Kochar bl bl1_main 67f3b4914bSYatharth Kochar 68f3b4914bSYatharth Kochar /* ----------------------------------------------------- 69f3b4914bSYatharth Kochar * Jump to next image. 70f3b4914bSYatharth Kochar * ----------------------------------------------------- 71f3b4914bSYatharth Kochar */ 72f3b4914bSYatharth Kochar 73f3b4914bSYatharth Kochar /* 74f3b4914bSYatharth Kochar * MMU needs to be disabled because both BL1 and BL2 execute 75f3b4914bSYatharth Kochar * in PL1, and therefore share the same address space. 76f3b4914bSYatharth Kochar * BL2 will initialize the address space according to its 77f3b4914bSYatharth Kochar * own requirement. 78f3b4914bSYatharth Kochar */ 79f3b4914bSYatharth Kochar bl disable_mmu_icache_secure 80f3b4914bSYatharth Kochar stcopr r0, TLBIALL 81f3b4914bSYatharth Kochar dsb sy 82f3b4914bSYatharth Kochar isb 83f3b4914bSYatharth Kochar 84f3b4914bSYatharth Kochar /* 85f3b4914bSYatharth Kochar * Get the smc_context for next BL image, 86f3b4914bSYatharth Kochar * program the gp/system registers and exit 87f3b4914bSYatharth Kochar * secure monitor mode 88f3b4914bSYatharth Kochar */ 89f3b4914bSYatharth Kochar bl smc_get_next_ctx 90*b6285d64SSoby Mathew monitor_exit 91f3b4914bSYatharth Kocharendfunc bl1_entrypoint 92