1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <context.h> 10 #include <context_mgmt.h> 11 #include <debug.h> 12 #include <platform.h> 13 #include <smcc_helpers.h> 14 15 /* 16 * Following arrays will be used for context management. 17 * There are 2 instances, for the Secure and Non-Secure contexts. 18 */ 19 static cpu_context_t bl1_cpu_context[2]; 20 static smc_ctx_t bl1_smc_context[2]; 21 22 /* Following contains the next cpu context pointer. */ 23 static void *bl1_next_cpu_context_ptr; 24 25 /* Following contains the next smc context pointer. */ 26 static void *bl1_next_smc_context_ptr; 27 28 /* Following functions are used for SMC context handling */ 29 void *smc_get_ctx(int security_state) 30 { 31 assert(sec_state_is_valid(security_state)); 32 return &bl1_smc_context[security_state]; 33 } 34 35 void smc_set_next_ctx(int security_state) 36 { 37 assert(sec_state_is_valid(security_state)); 38 bl1_next_smc_context_ptr = &bl1_smc_context[security_state]; 39 } 40 41 void *smc_get_next_ctx(void) 42 { 43 return bl1_next_smc_context_ptr; 44 } 45 46 /* Following functions are used for CPU context handling */ 47 void *cm_get_context(uint32_t security_state) 48 { 49 assert(sec_state_is_valid(security_state)); 50 return &bl1_cpu_context[security_state]; 51 } 52 53 void cm_set_next_context(void *cpu_context) 54 { 55 assert(cpu_context); 56 bl1_next_cpu_context_ptr = cpu_context; 57 } 58 59 void *cm_get_next_context(void) 60 { 61 return bl1_next_cpu_context_ptr; 62 } 63 64 /******************************************************************************* 65 * Following function copies GP regs r0-r4, lr and spsr, 66 * from the CPU context to the SMC context structures. 67 ******************************************************************************/ 68 static void copy_cpu_ctx_to_smc_ctx(const regs_t *cpu_reg_ctx, 69 smc_ctx_t *next_smc_ctx) 70 { 71 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0); 72 next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1); 73 next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2); 74 next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3); 75 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR); 76 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR); 77 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR); 78 } 79 80 /******************************************************************************* 81 * Following function flushes the SMC & CPU context pointer and its data. 82 ******************************************************************************/ 83 static void flush_smc_and_cpu_ctx(void) 84 { 85 flush_dcache_range((uintptr_t)&bl1_next_smc_context_ptr, 86 sizeof(bl1_next_smc_context_ptr)); 87 flush_dcache_range((uintptr_t)bl1_next_smc_context_ptr, 88 sizeof(smc_ctx_t)); 89 90 flush_dcache_range((uintptr_t)&bl1_next_cpu_context_ptr, 91 sizeof(bl1_next_cpu_context_ptr)); 92 flush_dcache_range((uintptr_t)bl1_next_cpu_context_ptr, 93 sizeof(cpu_context_t)); 94 } 95 96 /******************************************************************************* 97 * This function prepares the context for Secure/Normal world images. 98 * Normal world images are transitioned to HYP(if supported) else SVC. 99 ******************************************************************************/ 100 void bl1_prepare_next_image(unsigned int image_id) 101 { 102 unsigned int security_state; 103 image_desc_t *image_desc; 104 entry_point_info_t *next_bl_ep; 105 106 /* Get the image descriptor. */ 107 image_desc = bl1_plat_get_image_desc(image_id); 108 assert(image_desc); 109 110 /* Get the entry point info. */ 111 next_bl_ep = &image_desc->ep_info; 112 113 /* Get the image security state. */ 114 security_state = GET_SECURITY_STATE(next_bl_ep->h.attr); 115 116 /* Prepare the SPSR for the next BL image. */ 117 if (security_state == SECURE) { 118 next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, 119 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 120 } else { 121 /* Use HYP mode if supported else use SVC. */ 122 if (GET_VIRT_EXT(read_id_pfr1())) { 123 next_bl_ep->spsr = SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, 124 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 125 } else { 126 next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, 127 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 128 } 129 } 130 131 /* Allow platform to make change */ 132 bl1_plat_set_ep_info(image_id, next_bl_ep); 133 134 /* Prepare the cpu context for the next BL image. */ 135 cm_init_my_context(next_bl_ep); 136 cm_prepare_el3_exit(security_state); 137 cm_set_next_context(cm_get_context(security_state)); 138 139 /* Prepare the smc context for the next BL image. */ 140 smc_set_next_ctx(security_state); 141 copy_cpu_ctx_to_smc_ctx(get_regs_ctx(cm_get_next_context()), 142 smc_get_next_ctx()); 143 144 /* 145 * If the next image is non-secure, then we need to program the banked 146 * non secure sctlr. This is not required when the next image is secure 147 * because in AArch32, we expect the secure world to have the same 148 * SCTLR settings. 149 */ 150 if (security_state == NON_SECURE) { 151 cpu_context_t *ctx = cm_get_context(security_state); 152 u_register_t ns_sctlr; 153 154 /* Temporarily set the NS bit to access NS SCTLR */ 155 write_scr(read_scr() | SCR_NS_BIT); 156 isb(); 157 158 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR); 159 write_sctlr(ns_sctlr); 160 isb(); 161 162 write_scr(read_scr() & ~SCR_NS_BIT); 163 isb(); 164 } 165 166 /* 167 * Flush the SMC & CPU context and the (next)pointers, 168 * to access them after caches are disabled. 169 */ 170 flush_smc_and_cpu_ctx(); 171 172 /* Indicate that image is in execution state. */ 173 image_desc->state = IMAGE_STATE_EXECUTED; 174 175 print_entry_point_info(next_bl_ep); 176 } 177