1*4583de06SGatien Chevallier /* SPDX-License-Identifier: BSD-2-Clause */ 2*4583de06SGatien Chevallier /* 3*4583de06SGatien Chevallier * Copyright (C) 2022, STMicroelectronics - All Rights Reserved 4*4583de06SGatien Chevallier */ 5*4583de06SGatien Chevallier 6*4583de06SGatien Chevallier #ifndef __PTA_STM32MP_BSEC_H 7*4583de06SGatien Chevallier #define __PTA_STM32MP_BSEC_H 8*4583de06SGatien Chevallier 9*4583de06SGatien Chevallier #define PTA_BSEC_UUID { 0x94cf71ad, 0x80e6, 0x40b5, \ 10*4583de06SGatien Chevallier { 0xa7, 0xc6, 0x3d, 0xc5, 0x01, 0xeb, 0x28, 0x03 } } 11*4583de06SGatien Chevallier 12*4583de06SGatien Chevallier /** 13*4583de06SGatien Chevallier * Read OTP memory 14*4583de06SGatien Chevallier * 15*4583de06SGatien Chevallier * [in] value[0].a OTP start offset in byte 16*4583de06SGatien Chevallier * [in] value[0].b Access type, see PTA_BSEC_TYPE_* 17*4583de06SGatien Chevallier * [out] memref[1].buffer Output buffer to store read values 18*4583de06SGatien Chevallier * [out] memref[1].size Size of OTP to be read 19*4583de06SGatien Chevallier * 20*4583de06SGatien Chevallier * Return codes: 21*4583de06SGatien Chevallier * TEE_SUCCESS - Invoke command success 22*4583de06SGatien Chevallier * TEE_ERROR_BAD_PARAMETERS - Incorrect input param 23*4583de06SGatien Chevallier */ 24*4583de06SGatien Chevallier #define PTA_BSEC_CMD_READ_OTP 0x0 25*4583de06SGatien Chevallier 26*4583de06SGatien Chevallier /** 27*4583de06SGatien Chevallier * Write OTP memory 28*4583de06SGatien Chevallier * 29*4583de06SGatien Chevallier * [in] value[0].a OTP start offset in byte 30*4583de06SGatien Chevallier * [in] value[0].b Access type (0 : shadow, 31*4583de06SGatien Chevallier * 1 : fuse, 2 : lock) 32*4583de06SGatien Chevallier * [in] memref[1].buffer Input buffer to read values 33*4583de06SGatien Chevallier * [in] memref[1].size Size of OTP to be written 34*4583de06SGatien Chevallier * 35*4583de06SGatien Chevallier * Return codes: 36*4583de06SGatien Chevallier * TEE_SUCCESS - Invoke command success 37*4583de06SGatien Chevallier * TEE_ERROR_BAD_PARAMETERS - Incorrect input param 38*4583de06SGatien Chevallier * TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller 39*4583de06SGatien Chevallier */ 40*4583de06SGatien Chevallier #define PTA_BSEC_CMD_WRITE_OTP 0x1 41*4583de06SGatien Chevallier 42*4583de06SGatien Chevallier /** 43*4583de06SGatien Chevallier * Get BSEC state 44*4583de06SGatien Chevallier * Return the chip security level by reading the BSEC state 45*4583de06SGatien Chevallier * 46*4583de06SGatien Chevallier * [out] value[0].a One of PTA_BSEC_STATE_* 47*4583de06SGatien Chevallier * Return codes: 48*4583de06SGatien Chevallier * TEE_SUCCESS - Invoke command success 49*4583de06SGatien Chevallier * TEE_ERROR_BAD_PARAMETERS - Incorrect input param 50*4583de06SGatien Chevallier */ 51*4583de06SGatien Chevallier #define PTA_BSEC_CMD_GET_STATE 0x3 52*4583de06SGatien Chevallier 53*4583de06SGatien Chevallier enum stm32_bsec_pta_sec_state { 54*4583de06SGatien Chevallier PTA_BSEC_STATE_SEC_OPEN = 0, 55*4583de06SGatien Chevallier PTA_BSEC_STATE_SEC_CLOSE = 1, 56*4583de06SGatien Chevallier PTA_BSEC_STATE_INVALID = 3 57*4583de06SGatien Chevallier }; 58*4583de06SGatien Chevallier 59*4583de06SGatien Chevallier /* 60*4583de06SGatien Chevallier * Access types identifiers for PTA_BSEC_CMD_READ_OTP and 61*4583de06SGatien Chevallier * PTA_BSEC_CMD_WRITE_OTP = value[in].b. 62*4583de06SGatien Chevallier * 63*4583de06SGatien Chevallier * PTA_BSEC_SHADOW_ACCESS Access OTP shadow memory 64*4583de06SGatien Chevallier * PTA_BSEC_FUSE_ACCESS Access OTP fuse memory 65*4583de06SGatien Chevallier * PTA_BSEC_LOCKS_ACCESS Access OTP locks. The locks value read/written 66*4583de06SGatien Chevallier * in memref[1] 32bit words are related to bit flag 67*4583de06SGatien Chevallier * masks PTA_BSEC_LOCK_*. 68*4583de06SGatien Chevallier */ 69*4583de06SGatien Chevallier #define PTA_BSEC_SHADOW_ACCESS 0 70*4583de06SGatien Chevallier #define PTA_BSEC_FUSE_ACCESS 1 71*4583de06SGatien Chevallier #define PTA_BSEC_LOCKS_ACCESS 2 72*4583de06SGatien Chevallier 73*4583de06SGatien Chevallier /* 74*4583de06SGatien Chevallier * PTA_BSEC_LOCK_* - Bit mask of OTP locks in memref[1] 75*4583de06SGatien Chevallier * 76*4583de06SGatien Chevallier * PTA_BSEC_LOCK_PERM Fuse programming permanent lock 77*4583de06SGatien Chevallier * PTA_BSEC_LOCK_SHADOW_R Shadow programming (from fuse) lock 78*4583de06SGatien Chevallier * PTA_BSEC_LOCK_SHADOW_W Shadow memory write lock 79*4583de06SGatien Chevallier * PTA_BSEC_LOCK_SHADOW_P Fuse programming sticky lock 80*4583de06SGatien Chevallier * PTA_BSEC_LOCK_ERROR Flag indicating an error in lock access 81*4583de06SGatien Chevallier */ 82*4583de06SGatien Chevallier #define PTA_BSEC_LOCK_PERM BIT(30) 83*4583de06SGatien Chevallier #define PTA_BSEC_LOCK_SHADOW_R BIT(29) 84*4583de06SGatien Chevallier #define PTA_BSEC_LOCK_SHADOW_W BIT(28) 85*4583de06SGatien Chevallier #define PTA_BSEC_LOCK_SHADOW_P BIT(27) 86*4583de06SGatien Chevallier #define PTA_BSEC_LOCK_ERROR BIT(26) 87*4583de06SGatien Chevallier 88*4583de06SGatien Chevallier #endif /* __PTA_STM32MP_BSEC_H */ 89