11bb92983SJerome Forissier // SPDX-License-Identifier: BSD-2-Clause 27315b7b4SJens Wiklander /* 3e9f46c74SJens Wiklander * Copyright (c) 2016-2019, Linaro Limited 47315b7b4SJens Wiklander */ 57315b7b4SJens Wiklander 667729d8dSLudovic Barre #include <kernel/dt.h> 77315b7b4SJens Wiklander #include <kernel/interrupt.h> 8e9f46c74SJens Wiklander #include <kernel/panic.h> 967729d8dSLudovic Barre #include <libfdt.h> 10acc5dd21SLudovic Barre #include <stdlib.h> 117315b7b4SJens Wiklander #include <trace.h> 121c832d7cSdavidwang #include <assert.h> 137315b7b4SJens Wiklander 147315b7b4SJens Wiklander /* 157315b7b4SJens Wiklander * NOTE! 167315b7b4SJens Wiklander * 177315b7b4SJens Wiklander * We're assuming that there's no concurrent use of this interface, except 187315b7b4SJens Wiklander * delivery of interrupts in parallel. Synchronization will be needed when 197315b7b4SJens Wiklander * we begin to modify settings after boot initialization. 207315b7b4SJens Wiklander */ 217315b7b4SJens Wiklander 220c1be93bSVolodymyr Babchuk static struct itr_chip *itr_chip __nex_bss; 230c1be93bSVolodymyr Babchuk static SLIST_HEAD(, itr_handler) handlers __nex_data = 240c1be93bSVolodymyr Babchuk SLIST_HEAD_INITIALIZER(handlers); 257315b7b4SJens Wiklander 267315b7b4SJens Wiklander void itr_init(struct itr_chip *chip) 277315b7b4SJens Wiklander { 287315b7b4SJens Wiklander itr_chip = chip; 297315b7b4SJens Wiklander } 307315b7b4SJens Wiklander 3167729d8dSLudovic Barre #ifdef CFG_DT 3267729d8dSLudovic Barre int dt_get_irq(const void *fdt, int node) 3367729d8dSLudovic Barre { 3467729d8dSLudovic Barre const uint32_t *prop = NULL; 35*888bb63dSClément Léger int count = 0; 3667729d8dSLudovic Barre int it_num = DT_INFO_INVALID_INTERRUPT; 3767729d8dSLudovic Barre 3867729d8dSLudovic Barre if (!itr_chip || !itr_chip->dt_get_irq) 3967729d8dSLudovic Barre return it_num; 4067729d8dSLudovic Barre 41*888bb63dSClément Léger prop = fdt_getprop(fdt, node, "interrupts", &count); 4267729d8dSLudovic Barre if (!prop) 4367729d8dSLudovic Barre return it_num; 4467729d8dSLudovic Barre 45*888bb63dSClément Léger return itr_chip->dt_get_irq(prop, count); 4667729d8dSLudovic Barre } 4767729d8dSLudovic Barre #endif 4867729d8dSLudovic Barre 497315b7b4SJens Wiklander void itr_handle(size_t it) 507315b7b4SJens Wiklander { 511c832d7cSdavidwang struct itr_handler *h = NULL; 521c832d7cSdavidwang bool was_handled = false; 537315b7b4SJens Wiklander 541c832d7cSdavidwang SLIST_FOREACH(h, &handlers, link) { 551c832d7cSdavidwang if (h->it == it) { 561c832d7cSdavidwang if (h->handler(h) == ITRR_HANDLED) 571c832d7cSdavidwang was_handled = true; 581c832d7cSdavidwang else if (!(h->flags & ITRF_SHARED)) 591c832d7cSdavidwang break; 601c832d7cSdavidwang } 617315b7b4SJens Wiklander } 627315b7b4SJens Wiklander 631c832d7cSdavidwang if (!was_handled) { 641c832d7cSdavidwang EMSG("Disabling unhandled interrupt %zu", it); 657315b7b4SJens Wiklander itr_chip->ops->disable(itr_chip, it); 667315b7b4SJens Wiklander } 677315b7b4SJens Wiklander } 687315b7b4SJens Wiklander 69acc5dd21SLudovic Barre struct itr_handler *itr_alloc_add(size_t it, itr_handler_t handler, 70acc5dd21SLudovic Barre uint32_t flags, void *data) 71acc5dd21SLudovic Barre { 72acc5dd21SLudovic Barre struct itr_handler *hdl = calloc(1, sizeof(*hdl)); 73acc5dd21SLudovic Barre 74acc5dd21SLudovic Barre if (hdl) { 75acc5dd21SLudovic Barre hdl->it = it; 76acc5dd21SLudovic Barre hdl->handler = handler; 77acc5dd21SLudovic Barre hdl->flags = flags; 78acc5dd21SLudovic Barre hdl->data = data; 79acc5dd21SLudovic Barre itr_add(hdl); 80acc5dd21SLudovic Barre } 81acc5dd21SLudovic Barre 82acc5dd21SLudovic Barre return hdl; 83acc5dd21SLudovic Barre } 84acc5dd21SLudovic Barre 85acc5dd21SLudovic Barre void itr_free(struct itr_handler *hdl) 86acc5dd21SLudovic Barre { 87acc5dd21SLudovic Barre if (!hdl) 88acc5dd21SLudovic Barre return; 89acc5dd21SLudovic Barre 90acc5dd21SLudovic Barre itr_chip->ops->disable(itr_chip, hdl->it); 91acc5dd21SLudovic Barre 92acc5dd21SLudovic Barre SLIST_REMOVE(&handlers, hdl, itr_handler, link); 93acc5dd21SLudovic Barre free(hdl); 94acc5dd21SLudovic Barre } 95acc5dd21SLudovic Barre 967315b7b4SJens Wiklander void itr_add(struct itr_handler *h) 977315b7b4SJens Wiklander { 981c832d7cSdavidwang struct itr_handler __maybe_unused *hdl = NULL; 991c832d7cSdavidwang 1001c832d7cSdavidwang SLIST_FOREACH(hdl, &handlers, link) 1011c832d7cSdavidwang if (hdl->it == h->it) 1021c832d7cSdavidwang assert((hdl->flags & ITRF_SHARED) && 1031c832d7cSdavidwang (h->flags & ITRF_SHARED)); 1041c832d7cSdavidwang 1057315b7b4SJens Wiklander itr_chip->ops->add(itr_chip, h->it, h->flags); 1067315b7b4SJens Wiklander SLIST_INSERT_HEAD(&handlers, h, link); 1077315b7b4SJens Wiklander } 1087315b7b4SJens Wiklander 10926ed70ecSGuanchao Liang void itr_enable(size_t it) 1107315b7b4SJens Wiklander { 11126ed70ecSGuanchao Liang itr_chip->ops->enable(itr_chip, it); 1127315b7b4SJens Wiklander } 1137315b7b4SJens Wiklander 11426ed70ecSGuanchao Liang void itr_disable(size_t it) 1157315b7b4SJens Wiklander { 11626ed70ecSGuanchao Liang itr_chip->ops->disable(itr_chip, it); 11726ed70ecSGuanchao Liang } 11826ed70ecSGuanchao Liang 11926ed70ecSGuanchao Liang void itr_raise_pi(size_t it) 12026ed70ecSGuanchao Liang { 12126ed70ecSGuanchao Liang itr_chip->ops->raise_pi(itr_chip, it); 12226ed70ecSGuanchao Liang } 12326ed70ecSGuanchao Liang 12426ed70ecSGuanchao Liang void itr_raise_sgi(size_t it, uint8_t cpu_mask) 12526ed70ecSGuanchao Liang { 12626ed70ecSGuanchao Liang itr_chip->ops->raise_sgi(itr_chip, it, cpu_mask); 12726ed70ecSGuanchao Liang } 12826ed70ecSGuanchao Liang 12926ed70ecSGuanchao Liang void itr_set_affinity(size_t it, uint8_t cpu_mask) 13026ed70ecSGuanchao Liang { 13126ed70ecSGuanchao Liang itr_chip->ops->set_affinity(itr_chip, it, cpu_mask); 1327315b7b4SJens Wiklander } 133e9f46c74SJens Wiklander 134e9f46c74SJens Wiklander /* This function is supposed to be overridden in platform specific code */ 135e9f46c74SJens Wiklander void __weak __noreturn itr_core_handler(void) 136e9f46c74SJens Wiklander { 137e9f46c74SJens Wiklander panic("Secure interrupt handler not defined"); 138e9f46c74SJens Wiklander } 139