1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 #ifndef __MM_CORE_MMU_H 7 #define __MM_CORE_MMU_H 8 9 #ifndef __ASSEMBLER__ 10 #include <assert.h> 11 #include <compiler.h> 12 #include <kernel/user_ta.h> 13 #include <mm/tee_mm.h> 14 #include <mm/tee_mmu_types.h> 15 #include <types_ext.h> 16 #include <util.h> 17 #endif 18 19 #include <mm/core_mmu_arch.h> 20 #include <platform_config.h> 21 22 /* A small page is the smallest unit of memory that can be mapped */ 23 #define SMALL_PAGE_SIZE BIT(SMALL_PAGE_SHIFT) 24 #define SMALL_PAGE_MASK ((paddr_t)SMALL_PAGE_SIZE - 1) 25 26 /* 27 * PGDIR is the translation table above the translation table that holds 28 * the pages. 29 */ 30 #define CORE_MMU_PGDIR_SIZE BIT(CORE_MMU_PGDIR_SHIFT) 31 #define CORE_MMU_PGDIR_MASK ((paddr_t)CORE_MMU_PGDIR_SIZE - 1) 32 33 /* TA user space code, data, stack and heap are mapped using this granularity */ 34 #define CORE_MMU_USER_CODE_SIZE BIT(CORE_MMU_USER_CODE_SHIFT) 35 #define CORE_MMU_USER_CODE_MASK ((paddr_t)CORE_MMU_USER_CODE_SIZE - 1) 36 37 /* TA user space parameters are mapped using this granularity */ 38 #define CORE_MMU_USER_PARAM_SIZE BIT(CORE_MMU_USER_PARAM_SHIFT) 39 #define CORE_MMU_USER_PARAM_MASK ((paddr_t)CORE_MMU_USER_PARAM_SIZE - 1) 40 41 /* 42 * Identify mapping constraint: virtual base address is the physical start addr. 43 * If platform did not set some macros, some get default value. 44 */ 45 #ifndef TEE_RAM_VA_SIZE 46 #define TEE_RAM_VA_SIZE CORE_MMU_PGDIR_SIZE 47 #endif 48 49 #ifndef TEE_LOAD_ADDR 50 #define TEE_LOAD_ADDR TEE_RAM_START 51 #endif 52 53 #ifndef STACK_ALIGNMENT 54 #define STACK_ALIGNMENT (sizeof(long) * U(2)) 55 #endif 56 57 #ifndef __ASSEMBLER__ 58 /* 59 * Memory area type: 60 * MEM_AREA_TEE_RAM: core RAM (read/write/executable, secure, reserved to TEE) 61 * MEM_AREA_TEE_RAM_RX: core private read-only/executable memory (secure) 62 * MEM_AREA_TEE_RAM_RO: core private read-only/non-executable memory (secure) 63 * MEM_AREA_TEE_RAM_RW: core private read/write/non-executable memory (secure) 64 * MEM_AREA_INIT_RAM_RO: init private read-only/non-executable memory (secure) 65 * MEM_AREA_INIT_RAM_RX: init private read-only/executable memory (secure) 66 * MEM_AREA_NEX_RAM_RO: nexus private read-only/non-executable memory (secure) 67 * MEM_AREA_NEX_RAM_RW: nexus private r/w/non-executable memory (secure) 68 * MEM_AREA_TEE_COHERENT: teecore coherent RAM (secure, reserved to TEE) 69 * MEM_AREA_TEE_ASAN: core address sanitizer RAM (secure, reserved to TEE) 70 * MEM_AREA_IDENTITY_MAP_RX: core identity mapped r/o executable memory (secure) 71 * MEM_AREA_TA_RAM: Secure RAM where teecore loads/exec TA instances. 72 * MEM_AREA_NSEC_SHM: NonSecure shared RAM between NSec and TEE. 73 * MEM_AREA_NEX_NSEC_SHM: nexus non-secure shared RAM between NSec and TEE. 74 * MEM_AREA_RAM_NSEC: NonSecure RAM storing data 75 * MEM_AREA_RAM_SEC: Secure RAM storing some secrets 76 * MEM_AREA_ROM_SEC: Secure read only memory storing some secrets 77 * MEM_AREA_IO_NSEC: NonSecure HW mapped registers 78 * MEM_AREA_IO_SEC: Secure HW mapped registers 79 * MEM_AREA_EXT_DT: Memory loads external device tree 80 * MEM_AREA_MANIFEST_DT: Memory loads manifest device tree 81 * MEM_AREA_TRANSFER_LIST: Memory area mapped for Transfer List 82 * MEM_AREA_RES_VASPACE: Reserved virtual memory space 83 * MEM_AREA_SHM_VASPACE: Virtual memory space for dynamic shared memory buffers 84 * MEM_AREA_TS_VASPACE: TS va space, only used with phys_to_virt() 85 * MEM_AREA_DDR_OVERALL: Overall DDR address range, candidate to dynamic shm. 86 * MEM_AREA_SEC_RAM_OVERALL: Whole secure RAM 87 * MEM_AREA_MAXTYPE: lower invalid 'type' value 88 */ 89 enum teecore_memtypes { 90 MEM_AREA_TEE_RAM = 1, 91 MEM_AREA_TEE_RAM_RX, 92 MEM_AREA_TEE_RAM_RO, 93 MEM_AREA_TEE_RAM_RW, 94 MEM_AREA_INIT_RAM_RO, 95 MEM_AREA_INIT_RAM_RX, 96 MEM_AREA_NEX_RAM_RO, 97 MEM_AREA_NEX_RAM_RW, 98 MEM_AREA_TEE_COHERENT, 99 MEM_AREA_TEE_ASAN, 100 MEM_AREA_IDENTITY_MAP_RX, 101 MEM_AREA_TA_RAM, 102 MEM_AREA_NSEC_SHM, 103 MEM_AREA_NEX_NSEC_SHM, 104 MEM_AREA_RAM_NSEC, 105 MEM_AREA_RAM_SEC, 106 MEM_AREA_ROM_SEC, 107 MEM_AREA_IO_NSEC, 108 MEM_AREA_IO_SEC, 109 MEM_AREA_EXT_DT, 110 MEM_AREA_MANIFEST_DT, 111 MEM_AREA_TRANSFER_LIST, 112 MEM_AREA_RES_VASPACE, 113 MEM_AREA_SHM_VASPACE, 114 MEM_AREA_TS_VASPACE, 115 MEM_AREA_PAGER_VASPACE, 116 MEM_AREA_SDP_MEM, 117 MEM_AREA_DDR_OVERALL, 118 MEM_AREA_SEC_RAM_OVERALL, 119 MEM_AREA_MAXTYPE 120 }; 121 122 static inline const char *teecore_memtype_name(enum teecore_memtypes type) 123 { 124 static const char * const names[] = { 125 [MEM_AREA_TEE_RAM] = "TEE_RAM_RWX", 126 [MEM_AREA_TEE_RAM_RX] = "TEE_RAM_RX", 127 [MEM_AREA_TEE_RAM_RO] = "TEE_RAM_RO", 128 [MEM_AREA_TEE_RAM_RW] = "TEE_RAM_RW", 129 [MEM_AREA_INIT_RAM_RO] = "INIT_RAM_RO", 130 [MEM_AREA_INIT_RAM_RX] = "INIT_RAM_RX", 131 [MEM_AREA_NEX_RAM_RO] = "NEX_RAM_RO", 132 [MEM_AREA_NEX_RAM_RW] = "NEX_RAM_RW", 133 [MEM_AREA_TEE_ASAN] = "TEE_ASAN", 134 [MEM_AREA_IDENTITY_MAP_RX] = "IDENTITY_MAP_RX", 135 [MEM_AREA_TEE_COHERENT] = "TEE_COHERENT", 136 [MEM_AREA_TA_RAM] = "TA_RAM", 137 [MEM_AREA_NSEC_SHM] = "NSEC_SHM", 138 [MEM_AREA_NEX_NSEC_SHM] = "NEX_NSEC_SHM", 139 [MEM_AREA_RAM_NSEC] = "RAM_NSEC", 140 [MEM_AREA_RAM_SEC] = "RAM_SEC", 141 [MEM_AREA_ROM_SEC] = "ROM_SEC", 142 [MEM_AREA_IO_NSEC] = "IO_NSEC", 143 [MEM_AREA_IO_SEC] = "IO_SEC", 144 [MEM_AREA_EXT_DT] = "EXT_DT", 145 [MEM_AREA_MANIFEST_DT] = "MANIFEST_DT", 146 [MEM_AREA_TRANSFER_LIST] = "TRANSFER_LIST", 147 [MEM_AREA_RES_VASPACE] = "RES_VASPACE", 148 [MEM_AREA_SHM_VASPACE] = "SHM_VASPACE", 149 [MEM_AREA_TS_VASPACE] = "TS_VASPACE", 150 [MEM_AREA_PAGER_VASPACE] = "PAGER_VASPACE", 151 [MEM_AREA_SDP_MEM] = "SDP_MEM", 152 [MEM_AREA_DDR_OVERALL] = "DDR_OVERALL", 153 [MEM_AREA_SEC_RAM_OVERALL] = "SEC_RAM_OVERALL", 154 }; 155 156 COMPILE_TIME_ASSERT(ARRAY_SIZE(names) == MEM_AREA_MAXTYPE); 157 return names[type]; 158 } 159 160 #ifdef CFG_CORE_RWDATA_NOEXEC 161 #define MEM_AREA_TEE_RAM_RW_DATA MEM_AREA_TEE_RAM_RW 162 #else 163 #define MEM_AREA_TEE_RAM_RW_DATA MEM_AREA_TEE_RAM 164 #endif 165 166 struct core_mmu_phys_mem { 167 const char *name; 168 enum teecore_memtypes type; 169 __extension__ union { 170 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 171 struct { 172 uint32_t lo_addr; 173 uint32_t hi_addr; 174 }; 175 #endif 176 paddr_t addr; 177 }; 178 __extension__ union { 179 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 180 struct { 181 uint32_t lo_size; 182 uint32_t hi_size; 183 }; 184 #endif 185 paddr_size_t size; 186 }; 187 }; 188 189 #define __register_memory(_name, _type, _addr, _size, _section) \ 190 SCATTERED_ARRAY_DEFINE_ITEM(_section, struct core_mmu_phys_mem) = \ 191 { .name = (_name), .type = (_type), .addr = (_addr), \ 192 .size = (_size) } 193 194 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 195 #define __register_memory_ul(_name, _type, _addr, _size, _section) \ 196 SCATTERED_ARRAY_DEFINE_ITEM(_section, struct core_mmu_phys_mem) = \ 197 { .name = (_name), .type = (_type), .lo_addr = (_addr), \ 198 .lo_size = (_size) } 199 #else 200 #define __register_memory_ul(_name, _type, _addr, _size, _section) \ 201 __register_memory(_name, _type, _addr, _size, _section) 202 #endif 203 204 #define register_phys_mem(type, addr, size) \ 205 __register_memory(#addr, (type), (addr), (size), \ 206 phys_mem_map) 207 208 #define register_phys_mem_ul(type, addr, size) \ 209 __register_memory_ul(#addr, (type), (addr), (size), \ 210 phys_mem_map) 211 212 /* Same as register_phys_mem() but with PGDIR_SIZE granularity */ 213 #define register_phys_mem_pgdir(type, addr, size) \ 214 __register_memory(#addr, type, ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \ 215 ROUNDUP(size + addr - \ 216 ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \ 217 CORE_MMU_PGDIR_SIZE), phys_mem_map) 218 219 #ifdef CFG_SECURE_DATA_PATH 220 #define register_sdp_mem(addr, size) \ 221 __register_memory(#addr, MEM_AREA_SDP_MEM, (addr), (size), \ 222 phys_sdp_mem) 223 #else 224 #define register_sdp_mem(addr, size) \ 225 static int CONCAT(__register_sdp_mem_unused, __COUNTER__) \ 226 __unused 227 #endif 228 229 /* register_dynamic_shm() is deprecated, please use register_ddr() instead */ 230 #define register_dynamic_shm(addr, size) \ 231 __register_memory(#addr, MEM_AREA_DDR_OVERALL, (addr), (size), \ 232 phys_ddr_overall_compat) 233 234 /* 235 * register_ddr() - Define a memory range 236 * @addr: Base address 237 * @size: Length 238 * 239 * This macro can be used multiple times to define disjoint ranges. While 240 * initializing holes are carved out of these ranges where it overlaps with 241 * special memory, for instance memory registered with register_sdp_mem(). 242 * 243 * The memory that remains is accepted as non-secure shared memory when 244 * communicating with normal world. 245 * 246 * This macro is an alternative to supply the memory description with a 247 * devicetree blob. 248 */ 249 #define register_ddr(addr, size) \ 250 __register_memory(#addr, MEM_AREA_DDR_OVERALL, (addr), \ 251 (size), phys_ddr_overall) 252 253 #define phys_ddr_overall_begin \ 254 SCATTERED_ARRAY_BEGIN(phys_ddr_overall, struct core_mmu_phys_mem) 255 256 #define phys_ddr_overall_end \ 257 SCATTERED_ARRAY_END(phys_ddr_overall, struct core_mmu_phys_mem) 258 259 #define phys_ddr_overall_compat_begin \ 260 SCATTERED_ARRAY_BEGIN(phys_ddr_overall_compat, struct core_mmu_phys_mem) 261 262 #define phys_ddr_overall_compat_end \ 263 SCATTERED_ARRAY_END(phys_ddr_overall_compat, struct core_mmu_phys_mem) 264 265 #define phys_sdp_mem_begin \ 266 SCATTERED_ARRAY_BEGIN(phys_sdp_mem, struct core_mmu_phys_mem) 267 268 #define phys_sdp_mem_end \ 269 SCATTERED_ARRAY_END(phys_sdp_mem, struct core_mmu_phys_mem) 270 271 #define phys_mem_map_begin \ 272 SCATTERED_ARRAY_BEGIN(phys_mem_map, struct core_mmu_phys_mem) 273 274 #define phys_mem_map_end \ 275 SCATTERED_ARRAY_END(phys_mem_map, struct core_mmu_phys_mem) 276 277 /* Virtual memory pool for core mappings */ 278 extern tee_mm_pool_t core_virt_mem_pool; 279 280 /* Virtual memory pool for shared memory mappings */ 281 extern tee_mm_pool_t core_virt_shm_pool; 282 283 #ifdef CFG_CORE_RESERVED_SHM 284 /* Default NSec shared memory allocated from NSec world */ 285 extern unsigned long default_nsec_shm_paddr; 286 extern unsigned long default_nsec_shm_size; 287 #endif 288 289 /* 290 * Physical load address of OP-TEE updated during boot if needed to reflect 291 * the value used. 292 */ 293 #ifdef CFG_CORE_PHYS_RELOCATABLE 294 extern unsigned long core_mmu_tee_load_pa; 295 #else 296 extern const unsigned long core_mmu_tee_load_pa; 297 #endif 298 299 void core_init_mmu_map(unsigned long seed, struct core_mmu_config *cfg); 300 void core_init_mmu_regs(struct core_mmu_config *cfg); 301 302 /* Arch specific function to help optimizing 1 MMU xlat table */ 303 bool core_mmu_prefer_tee_ram_at_top(paddr_t paddr); 304 305 /* 306 * struct mmu_partition - stores MMU partition. 307 * 308 * Basically it represent whole MMU mapping. It is possible 309 * to create multiple partitions, and change them in runtime, 310 * effectively changing how OP-TEE sees memory. 311 * This is opaque struct which is defined differently for 312 * v7 and LPAE MMUs 313 * 314 * This structure used mostly when virtualization is enabled. 315 * When CFG_NS_VIRTUALIZATION==n only default partition exists. 316 */ 317 struct mmu_partition; 318 319 /* 320 * core_mmu_get_user_va_range() - Return range of user va space 321 * @base: Lowest user virtual address 322 * @size: Size in bytes of user address space 323 */ 324 void core_mmu_get_user_va_range(vaddr_t *base, size_t *size); 325 326 /* 327 * enum core_mmu_fault - different kinds of faults 328 * @CORE_MMU_FAULT_ALIGNMENT: alignment fault 329 * @CORE_MMU_FAULT_DEBUG_EVENT: debug event 330 * @CORE_MMU_FAULT_TRANSLATION: translation fault 331 * @CORE_MMU_FAULT_WRITE_PERMISSION: Permission fault during write 332 * @CORE_MMU_FAULT_READ_PERMISSION: Permission fault during read 333 * @CORE_MMU_FAULT_ASYNC_EXTERNAL: asynchronous external abort 334 * @CORE_MMU_FAULT_ACCESS_BIT: access bit fault 335 * @CORE_MMU_FAULT_TAG_CHECK: tag check fault 336 * @CORE_MMU_FAULT_OTHER: Other/unknown fault 337 */ 338 enum core_mmu_fault { 339 CORE_MMU_FAULT_ALIGNMENT, 340 CORE_MMU_FAULT_DEBUG_EVENT, 341 CORE_MMU_FAULT_TRANSLATION, 342 CORE_MMU_FAULT_WRITE_PERMISSION, 343 CORE_MMU_FAULT_READ_PERMISSION, 344 CORE_MMU_FAULT_ASYNC_EXTERNAL, 345 CORE_MMU_FAULT_ACCESS_BIT, 346 CORE_MMU_FAULT_TAG_CHECK, 347 CORE_MMU_FAULT_OTHER, 348 }; 349 350 /* 351 * core_mmu_get_fault_type() - get fault type 352 * @fault_descr: Content of fault status or exception syndrome register 353 * @returns an enum describing the content of fault status register. 354 */ 355 enum core_mmu_fault core_mmu_get_fault_type(uint32_t fault_descr); 356 357 /* 358 * core_mm_type_to_attr() - convert memory type to attribute 359 * @t: memory type 360 * @returns an attribute that can be passed to core_mm_set_entry() and friends 361 */ 362 uint32_t core_mmu_type_to_attr(enum teecore_memtypes t); 363 364 /* 365 * core_mmu_create_user_map() - Create user mode mapping 366 * @uctx: Pointer to user mode context 367 * @map: MMU configuration to use when activating this VA space 368 */ 369 void core_mmu_create_user_map(struct user_mode_ctx *uctx, 370 struct core_mmu_user_map *map); 371 /* 372 * core_mmu_get_user_map() - Reads current MMU configuration for user VA space 373 * @map: MMU configuration for current user VA space. 374 */ 375 void core_mmu_get_user_map(struct core_mmu_user_map *map); 376 377 /* 378 * core_mmu_set_user_map() - Set new MMU configuration for user VA space 379 * @map: User context MMU configuration or NULL to set core VA space 380 * 381 * Activate user VA space mapping and set its ASID if @map is not NULL, 382 * otherwise activate core mapping and set ASID to 0. 383 */ 384 void core_mmu_set_user_map(struct core_mmu_user_map *map); 385 386 /* 387 * struct core_mmu_table_info - Properties for a translation table 388 * @table: Pointer to translation table 389 * @va_base: VA base address of the transaltion table 390 * @level: Translation table level 391 * @next_level: Finer grained translation table level according to @level. 392 * @shift: The shift of each entry in the table 393 * @num_entries: Number of entries in this table. 394 */ 395 struct core_mmu_table_info { 396 void *table; 397 vaddr_t va_base; 398 unsigned num_entries; 399 #ifdef CFG_NS_VIRTUALIZATION 400 struct mmu_partition *prtn; 401 #endif 402 uint8_t level; 403 uint8_t shift; 404 uint8_t next_level; 405 }; 406 407 /* 408 * core_mmu_find_table() - Locates a translation table 409 * @prtn: MMU partition where search should be performed 410 * @va: Virtual address for the table to cover 411 * @max_level: Don't traverse beyond this level 412 * @tbl_info: Pointer to where to store properties. 413 * @return true if a translation table was found, false on error 414 */ 415 bool core_mmu_find_table(struct mmu_partition *prtn, vaddr_t va, 416 unsigned max_level, 417 struct core_mmu_table_info *tbl_info); 418 419 /* 420 * core_mmu_entry_to_finer_grained() - divide mapping at current level into 421 * smaller ones so memory can be mapped with finer granularity 422 * @tbl_info: table where target record located 423 * @idx: index of record for which a pdgir must be setup. 424 * @secure: true/false if pgdir maps secure/non-secure memory (32bit mmu) 425 * @return true on successful, false on error 426 */ 427 bool core_mmu_entry_to_finer_grained(struct core_mmu_table_info *tbl_info, 428 unsigned int idx, bool secure); 429 430 void core_mmu_set_entry_primitive(void *table, size_t level, size_t idx, 431 paddr_t pa, uint32_t attr); 432 433 void core_mmu_get_user_pgdir(struct core_mmu_table_info *pgd_info); 434 435 /* 436 * core_mmu_set_entry() - Set entry in translation table 437 * @tbl_info: Translation table properties 438 * @idx: Index of entry to update 439 * @pa: Physical address to assign entry 440 * @attr: Attributes to assign entry 441 */ 442 void core_mmu_set_entry(struct core_mmu_table_info *tbl_info, unsigned idx, 443 paddr_t pa, uint32_t attr); 444 445 void core_mmu_get_entry_primitive(const void *table, size_t level, size_t idx, 446 paddr_t *pa, uint32_t *attr); 447 448 /* 449 * core_mmu_get_entry() - Get entry from translation table 450 * @tbl_info: Translation table properties 451 * @idx: Index of entry to read 452 * @pa: Physical address is returned here if pa is not NULL 453 * @attr: Attributues are returned here if attr is not NULL 454 */ 455 void core_mmu_get_entry(struct core_mmu_table_info *tbl_info, unsigned idx, 456 paddr_t *pa, uint32_t *attr); 457 458 /* 459 * core_mmu_va2idx() - Translate from virtual address to table index 460 * @tbl_info: Translation table properties 461 * @va: Virtual address to translate 462 * @returns index in transaltion table 463 */ 464 static inline unsigned core_mmu_va2idx(struct core_mmu_table_info *tbl_info, 465 vaddr_t va) 466 { 467 return (va - tbl_info->va_base) >> tbl_info->shift; 468 } 469 470 /* 471 * core_mmu_idx2va() - Translate from table index to virtual address 472 * @tbl_info: Translation table properties 473 * @idx: Index to translate 474 * @returns Virtual address 475 */ 476 static inline vaddr_t core_mmu_idx2va(struct core_mmu_table_info *tbl_info, 477 unsigned idx) 478 { 479 return (idx << tbl_info->shift) + tbl_info->va_base; 480 } 481 482 /* 483 * core_mmu_get_block_offset() - Get offset inside a block/page 484 * @tbl_info: Translation table properties 485 * @pa: Physical address 486 * @returns offset within one block of the translation table 487 */ 488 static inline size_t core_mmu_get_block_offset( 489 struct core_mmu_table_info *tbl_info, paddr_t pa) 490 { 491 return pa & ((1 << tbl_info->shift) - 1); 492 } 493 494 /* 495 * core_mmu_is_dynamic_vaspace() - Check if memory region belongs to 496 * empty virtual address space that is used for dymanic mappings 497 * @mm: memory region to be checked 498 * @returns result of the check 499 */ 500 static inline bool core_mmu_is_dynamic_vaspace(struct tee_mmap_region *mm) 501 { 502 return mm->type == MEM_AREA_RES_VASPACE || 503 mm->type == MEM_AREA_SHM_VASPACE; 504 } 505 506 /* 507 * core_mmu_map_pages() - map list of pages at given virtual address 508 * @vstart: Virtual address where mapping begins 509 * @pages: Array of page addresses 510 * @num_pages: Number of pages 511 * @memtype: Type of memmory to be mapped 512 * 513 * Note: This function asserts that pages are not mapped executeable for 514 * kernel (privileged) mode. 515 * 516 * @returns: TEE_SUCCESS on success, TEE_ERROR_XXX on error 517 */ 518 TEE_Result core_mmu_map_pages(vaddr_t vstart, paddr_t *pages, size_t num_pages, 519 enum teecore_memtypes memtype); 520 521 /* 522 * core_mmu_map_contiguous_pages() - map range of pages at given virtual address 523 * @vstart: Virtual address where mapping begins 524 * @pstart: Physical address of the first page 525 * @num_pages: Number of pages 526 * @memtype: Type of memmory to be mapped 527 * 528 * Note: This function asserts that pages are not mapped executeable for 529 * kernel (privileged) mode. 530 * 531 * @returns: TEE_SUCCESS on success, TEE_ERROR_XXX on error 532 */ 533 TEE_Result core_mmu_map_contiguous_pages(vaddr_t vstart, paddr_t pstart, 534 size_t num_pages, 535 enum teecore_memtypes memtype); 536 537 /* 538 * core_mmu_unmap_pages() - remove mapping at given virtual address 539 * @vstart: Virtual address where mapping begins 540 * @num_pages: Number of pages to unmap 541 */ 542 void core_mmu_unmap_pages(vaddr_t vstart, size_t num_pages); 543 544 /* 545 * core_mmu_user_mapping_is_active() - Report if user mapping is active 546 * @returns true if a user VA space is active, false if user VA space is 547 * inactive. 548 */ 549 bool core_mmu_user_mapping_is_active(void); 550 551 /* 552 * core_mmu_user_va_range_is_defined() - check if user va range is defined 553 * @returns true if a user VA space is defined, false if not. 554 */ 555 bool core_mmu_user_va_range_is_defined(void); 556 557 /* 558 * core_mmu_mattr_is_ok() - Check that supplied mem attributes can be used 559 * @returns true if the attributes can be used, false if not. 560 */ 561 bool core_mmu_mattr_is_ok(uint32_t mattr); 562 563 TEE_Result core_mmu_for_each_map(void *ptr, 564 TEE_Result (*fn)(struct tee_mmap_region *map, 565 void *ptr)); 566 567 void core_mmu_get_mem_by_type(enum teecore_memtypes type, vaddr_t *s, 568 vaddr_t *e); 569 570 enum teecore_memtypes core_mmu_get_type_by_pa(paddr_t pa); 571 572 /* routines to retreive shared mem configuration */ 573 static inline bool core_mmu_is_shm_cached(void) 574 { 575 return mattr_is_cached(core_mmu_type_to_attr(MEM_AREA_NSEC_SHM)); 576 } 577 578 TEE_Result core_mmu_remove_mapping(enum teecore_memtypes type, void *addr, 579 size_t len); 580 void *core_mmu_add_mapping(enum teecore_memtypes type, paddr_t addr, 581 size_t len); 582 583 /* 584 * core_mmu_find_mapping_exclusive() - Find mapping of specified type and 585 * length. If more than one mapping of 586 * specified type is present, NULL will be 587 * returned. 588 * @type: memory type 589 * @len: length in bytes 590 */ 591 struct tee_mmap_region * 592 core_mmu_find_mapping_exclusive(enum teecore_memtypes type, size_t len); 593 594 /* 595 * tlbi_va_range() - Invalidate TLB for virtual address range 596 * @va: start virtual address, must be a multiple of @granule 597 * @len: length in bytes of range, must be a multiple of @granule 598 * @granule: granularity of mapping, supported values are 599 * CORE_MMU_PGDIR_SIZE or SMALL_PAGE_SIZE. This value must 600 * match the actual mappings. 601 */ 602 void tlbi_va_range(vaddr_t va, size_t len, size_t granule); 603 604 /* 605 * tlbi_va_range_asid() - Invalidate TLB for virtual address range for 606 * a specific ASID 607 * @va: start virtual address, must be a multiple of @granule 608 * @len: length in bytes of range, must be a multiple of @granule 609 * @granule: granularity of mapping, supported values are 610 * CORE_MMU_PGDIR_SIZE or SMALL_PAGE_SIZE. This value must 611 * match the actual mappings. 612 * @asid: Address space identifier 613 */ 614 void tlbi_va_range_asid(vaddr_t va, size_t len, size_t granule, uint32_t asid); 615 616 /* Check cpu mmu enabled or not */ 617 bool cpu_mmu_enabled(void); 618 619 #ifdef CFG_CORE_DYN_SHM 620 /* 621 * Check if platform defines nsec DDR range(s). 622 * Static SHM (MEM_AREA_NSEC_SHM) is not covered by this API as it is 623 * always present. 624 */ 625 bool core_mmu_nsec_ddr_is_defined(void); 626 627 void core_mmu_set_discovered_nsec_ddr(struct core_mmu_phys_mem *start, 628 size_t nelems); 629 #endif 630 631 /* Initialize MMU partition */ 632 void core_init_mmu_prtn(struct mmu_partition *prtn, struct memory_map *mem_map); 633 634 unsigned int asid_alloc(void); 635 void asid_free(unsigned int asid); 636 637 #ifdef CFG_SECURE_DATA_PATH 638 /* Alloc and fill SDP memory objects table - table is NULL terminated */ 639 struct mobj **core_sdp_mem_create_mobjs(void); 640 #endif 641 642 #ifdef CFG_NS_VIRTUALIZATION 643 size_t core_mmu_get_total_pages_size(void); 644 struct mmu_partition *core_alloc_mmu_prtn(void *tables); 645 void core_free_mmu_prtn(struct mmu_partition *prtn); 646 void core_mmu_set_prtn(struct mmu_partition *prtn); 647 void core_mmu_set_default_prtn(void); 648 void core_mmu_set_default_prtn_tbl(void); 649 #endif 650 651 void core_mmu_init_virtualization(void); 652 653 /* Initialize physical memory pool */ 654 void core_mmu_init_phys_mem(void); 655 656 void core_init_mmu(struct memory_map *mem_map); 657 658 void core_mmu_set_info_table(struct core_mmu_table_info *tbl_info, 659 unsigned int level, vaddr_t va_base, void *table); 660 void core_mmu_populate_user_map(struct core_mmu_table_info *dir_info, 661 struct user_mode_ctx *uctx); 662 void core_mmu_map_region(struct mmu_partition *prtn, 663 struct tee_mmap_region *mm); 664 665 bool arch_va2pa_helper(void *va, paddr_t *pa); 666 667 static inline bool core_mmu_check_end_pa(paddr_t pa, size_t len) 668 { 669 paddr_t end_pa = 0; 670 671 if (ADD_OVERFLOW(pa, len - 1, &end_pa)) 672 return false; 673 return core_mmu_check_max_pa(end_pa); 674 } 675 676 /* 677 * core_mmu_set_secure_memory() - set physical secure memory range 678 * @base: base address of secure memory 679 * @size: size of secure memory 680 * 681 * The physical secure memory range is not known in advance when OP-TEE is 682 * relocatable, this information must be supplied once during boot before 683 * the translation tables can be initialized and the MMU enabled. 684 */ 685 void core_mmu_set_secure_memory(paddr_t base, size_t size); 686 687 /* 688 * core_mmu_get_secure_memory() - get physical secure memory range 689 * @base: base address of secure memory 690 * @size: size of secure memory 691 * 692 * The physical secure memory range returned covers at least the memory 693 * range used by OP-TEE Core, but may cover more memory depending on the 694 * configuration. 695 */ 696 void core_mmu_get_secure_memory(paddr_t *base, paddr_size_t *size); 697 698 /* 699 * core_mmu_get_ta_range() - get physical memory range reserved for TAs 700 * @base: [out] range base address ref or NULL 701 * @size: [out] range size ref or NULL 702 */ 703 void core_mmu_get_ta_range(paddr_t *base, size_t *size); 704 705 #endif /*__ASSEMBLER__*/ 706 707 #endif /* __MM_CORE_MMU_H */ 708