1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 #ifndef CORE_MMU_H 7 #define CORE_MMU_H 8 9 #ifndef __ASSEMBLER__ 10 #include <assert.h> 11 #include <compiler.h> 12 #include <kernel/user_ta.h> 13 #include <mm/tee_mmu_types.h> 14 #include <types_ext.h> 15 #include <util.h> 16 #endif 17 18 #include <mm/core_mmu_arch.h> 19 #include <platform_config.h> 20 21 /* A small page is the smallest unit of memory that can be mapped */ 22 #define SMALL_PAGE_SIZE BIT(SMALL_PAGE_SHIFT) 23 #define SMALL_PAGE_MASK ((paddr_t)SMALL_PAGE_SIZE - 1) 24 25 /* 26 * PGDIR is the translation table above the translation table that holds 27 * the pages. 28 */ 29 #define CORE_MMU_PGDIR_SIZE BIT(CORE_MMU_PGDIR_SHIFT) 30 #define CORE_MMU_PGDIR_MASK ((paddr_t)CORE_MMU_PGDIR_SIZE - 1) 31 32 /* TA user space code, data, stack and heap are mapped using this granularity */ 33 #define CORE_MMU_USER_CODE_SIZE BIT(CORE_MMU_USER_CODE_SHIFT) 34 #define CORE_MMU_USER_CODE_MASK ((paddr_t)CORE_MMU_USER_CODE_SIZE - 1) 35 36 /* TA user space parameters are mapped using this granularity */ 37 #define CORE_MMU_USER_PARAM_SIZE BIT(CORE_MMU_USER_PARAM_SHIFT) 38 #define CORE_MMU_USER_PARAM_MASK ((paddr_t)CORE_MMU_USER_PARAM_SIZE - 1) 39 40 /* 41 * Identify mapping constraint: virtual base address is the physical start addr. 42 * If platform did not set some macros, some get default value. 43 */ 44 #ifndef TEE_RAM_VA_SIZE 45 #define TEE_RAM_VA_SIZE CORE_MMU_PGDIR_SIZE 46 #endif 47 48 #ifndef TEE_LOAD_ADDR 49 #define TEE_LOAD_ADDR TEE_RAM_START 50 #endif 51 52 #define TEE_RAM_VA_START TEE_RAM_START 53 #define TEE_TEXT_VA_START (TEE_RAM_VA_START + \ 54 (TEE_LOAD_ADDR - TEE_RAM_START)) 55 56 #ifndef STACK_ALIGNMENT 57 #define STACK_ALIGNMENT (sizeof(long) * U(2)) 58 #endif 59 60 #ifndef __ASSEMBLER__ 61 /* 62 * Memory area type: 63 * MEM_AREA_END: Reserved, marks the end of a table of mapping areas. 64 * MEM_AREA_TEE_RAM: core RAM (read/write/executable, secure, reserved to TEE) 65 * MEM_AREA_TEE_RAM_RX: core private read-only/executable memory (secure) 66 * MEM_AREA_TEE_RAM_RO: core private read-only/non-executable memory (secure) 67 * MEM_AREA_TEE_RAM_RW: core private read/write/non-executable memory (secure) 68 * MEM_AREA_INIT_RAM_RO: init private read-only/non-executable memory (secure) 69 * MEM_AREA_INIT_RAM_RX: init private read-only/executable memory (secure) 70 * MEM_AREA_NEX_RAM_RO: nexus private read-only/non-executable memory (secure) 71 * MEM_AREA_NEX_RAM_RW: nexus private r/w/non-executable memory (secure) 72 * MEM_AREA_TEE_COHERENT: teecore coherent RAM (secure, reserved to TEE) 73 * MEM_AREA_TEE_ASAN: core address sanitizer RAM (secure, reserved to TEE) 74 * MEM_AREA_IDENTITY_MAP_RX: core identity mapped r/o executable memory (secure) 75 * MEM_AREA_TA_RAM: Secure RAM where teecore loads/exec TA instances. 76 * MEM_AREA_NSEC_SHM: NonSecure shared RAM between NSec and TEE. 77 * MEM_AREA_RAM_NSEC: NonSecure RAM storing data 78 * MEM_AREA_RAM_SEC: Secure RAM storing some secrets 79 * MEM_AREA_IO_NSEC: NonSecure HW mapped registers 80 * MEM_AREA_IO_SEC: Secure HW mapped registers 81 * MEM_AREA_EXT_DT: Memory loads external device tree 82 * MEM_AREA_RES_VASPACE: Reserved virtual memory space 83 * MEM_AREA_SHM_VASPACE: Virtual memory space for dynamic shared memory buffers 84 * MEM_AREA_TS_VASPACE: TS va space, only used with phys_to_virt() 85 * MEM_AREA_DDR_OVERALL: Overall DDR address range, candidate to dynamic shm. 86 * MEM_AREA_SEC_RAM_OVERALL: Whole secure RAM 87 * MEM_AREA_MAXTYPE: lower invalid 'type' value 88 */ 89 enum teecore_memtypes { 90 MEM_AREA_END = 0, 91 MEM_AREA_TEE_RAM, 92 MEM_AREA_TEE_RAM_RX, 93 MEM_AREA_TEE_RAM_RO, 94 MEM_AREA_TEE_RAM_RW, 95 MEM_AREA_INIT_RAM_RO, 96 MEM_AREA_INIT_RAM_RX, 97 MEM_AREA_NEX_RAM_RO, 98 MEM_AREA_NEX_RAM_RW, 99 MEM_AREA_TEE_COHERENT, 100 MEM_AREA_TEE_ASAN, 101 MEM_AREA_IDENTITY_MAP_RX, 102 MEM_AREA_TA_RAM, 103 MEM_AREA_NSEC_SHM, 104 MEM_AREA_RAM_NSEC, 105 MEM_AREA_RAM_SEC, 106 MEM_AREA_IO_NSEC, 107 MEM_AREA_IO_SEC, 108 MEM_AREA_EXT_DT, 109 MEM_AREA_RES_VASPACE, 110 MEM_AREA_SHM_VASPACE, 111 MEM_AREA_TS_VASPACE, 112 MEM_AREA_PAGER_VASPACE, 113 MEM_AREA_SDP_MEM, 114 MEM_AREA_DDR_OVERALL, 115 MEM_AREA_SEC_RAM_OVERALL, 116 MEM_AREA_MAXTYPE 117 }; 118 119 static inline const char *teecore_memtype_name(enum teecore_memtypes type) 120 { 121 static const char * const names[] = { 122 [MEM_AREA_END] = "END", 123 [MEM_AREA_TEE_RAM] = "TEE_RAM_RWX", 124 [MEM_AREA_TEE_RAM_RX] = "TEE_RAM_RX", 125 [MEM_AREA_TEE_RAM_RO] = "TEE_RAM_RO", 126 [MEM_AREA_TEE_RAM_RW] = "TEE_RAM_RW", 127 [MEM_AREA_INIT_RAM_RO] = "INIT_RAM_RO", 128 [MEM_AREA_INIT_RAM_RX] = "INIT_RAM_RX", 129 [MEM_AREA_NEX_RAM_RO] = "NEX_RAM_RO", 130 [MEM_AREA_NEX_RAM_RW] = "NEX_RAM_RW", 131 [MEM_AREA_TEE_ASAN] = "TEE_ASAN", 132 [MEM_AREA_IDENTITY_MAP_RX] = "IDENTITY_MAP_RX", 133 [MEM_AREA_TEE_COHERENT] = "TEE_COHERENT", 134 [MEM_AREA_TA_RAM] = "TA_RAM", 135 [MEM_AREA_NSEC_SHM] = "NSEC_SHM", 136 [MEM_AREA_RAM_NSEC] = "RAM_NSEC", 137 [MEM_AREA_RAM_SEC] = "RAM_SEC", 138 [MEM_AREA_IO_NSEC] = "IO_NSEC", 139 [MEM_AREA_IO_SEC] = "IO_SEC", 140 [MEM_AREA_EXT_DT] = "EXT_DT", 141 [MEM_AREA_RES_VASPACE] = "RES_VASPACE", 142 [MEM_AREA_SHM_VASPACE] = "SHM_VASPACE", 143 [MEM_AREA_TS_VASPACE] = "TS_VASPACE", 144 [MEM_AREA_PAGER_VASPACE] = "PAGER_VASPACE", 145 [MEM_AREA_SDP_MEM] = "SDP_MEM", 146 [MEM_AREA_DDR_OVERALL] = "DDR_OVERALL", 147 [MEM_AREA_SEC_RAM_OVERALL] = "SEC_RAM_OVERALL", 148 }; 149 150 COMPILE_TIME_ASSERT(ARRAY_SIZE(names) == MEM_AREA_MAXTYPE); 151 return names[type]; 152 } 153 154 #ifdef CFG_CORE_RWDATA_NOEXEC 155 #define MEM_AREA_TEE_RAM_RW_DATA MEM_AREA_TEE_RAM_RW 156 #else 157 #define MEM_AREA_TEE_RAM_RW_DATA MEM_AREA_TEE_RAM 158 #endif 159 160 struct core_mmu_phys_mem { 161 const char *name; 162 enum teecore_memtypes type; 163 __extension__ union { 164 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 165 struct { 166 uint32_t lo_addr; 167 uint32_t hi_addr; 168 }; 169 #endif 170 paddr_t addr; 171 }; 172 __extension__ union { 173 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 174 struct { 175 uint32_t lo_size; 176 uint32_t hi_size; 177 }; 178 #endif 179 paddr_size_t size; 180 }; 181 }; 182 183 #define __register_memory(_name, _type, _addr, _size, _section) \ 184 SCATTERED_ARRAY_DEFINE_ITEM(_section, struct core_mmu_phys_mem) = \ 185 { .name = (_name), .type = (_type), .addr = (_addr), \ 186 .size = (_size) } 187 188 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 189 #define __register_memory_ul(_name, _type, _addr, _size, _section) \ 190 SCATTERED_ARRAY_DEFINE_ITEM(_section, struct core_mmu_phys_mem) = \ 191 { .name = (_name), .type = (_type), .lo_addr = (_addr), \ 192 .lo_size = (_size) } 193 #else 194 #define __register_memory_ul(_name, _type, _addr, _size, _section) \ 195 __register_memory(_name, _type, _addr, _size, _section) 196 #endif 197 198 #define register_phys_mem(type, addr, size) \ 199 __register_memory(#addr, (type), (addr), (size), \ 200 phys_mem_map) 201 202 #define register_phys_mem_ul(type, addr, size) \ 203 __register_memory_ul(#addr, (type), (addr), (size), \ 204 phys_mem_map) 205 206 /* Same as register_phys_mem() but with PGDIR_SIZE granularity */ 207 #define register_phys_mem_pgdir(type, addr, size) \ 208 __register_memory(#addr, type, ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \ 209 ROUNDUP(size + addr - \ 210 ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \ 211 CORE_MMU_PGDIR_SIZE), phys_mem_map) 212 213 #ifdef CFG_SECURE_DATA_PATH 214 #define register_sdp_mem(addr, size) \ 215 __register_memory(#addr, MEM_AREA_SDP_MEM, (addr), (size), \ 216 phys_sdp_mem) 217 #else 218 #define register_sdp_mem(addr, size) \ 219 static int CONCAT(__register_sdp_mem_unused, __COUNTER__) \ 220 __unused 221 #endif 222 223 /* register_dynamic_shm() is deprecated, please use register_ddr() instead */ 224 #define register_dynamic_shm(addr, size) \ 225 __register_memory(#addr, MEM_AREA_DDR_OVERALL, (addr), (size), \ 226 phys_ddr_overall_compat) 227 228 /* 229 * register_ddr() - Define a memory range 230 * @addr: Base address 231 * @size: Length 232 * 233 * This macro can be used multiple times to define disjoint ranges. While 234 * initializing holes are carved out of these ranges where it overlaps with 235 * special memory, for instance memory registered with register_sdp_mem(). 236 * 237 * The memory that remains is accepted as non-secure shared memory when 238 * communicating with normal world. 239 * 240 * This macro is an alternative to supply the memory description with a 241 * devicetree blob. 242 */ 243 #define register_ddr(addr, size) \ 244 __register_memory(#addr, MEM_AREA_DDR_OVERALL, (addr), \ 245 (size), phys_ddr_overall) 246 247 #define phys_ddr_overall_begin \ 248 SCATTERED_ARRAY_BEGIN(phys_ddr_overall, struct core_mmu_phys_mem) 249 250 #define phys_ddr_overall_end \ 251 SCATTERED_ARRAY_END(phys_ddr_overall, struct core_mmu_phys_mem) 252 253 #define phys_ddr_overall_compat_begin \ 254 SCATTERED_ARRAY_BEGIN(phys_ddr_overall_compat, struct core_mmu_phys_mem) 255 256 #define phys_ddr_overall_compat_end \ 257 SCATTERED_ARRAY_END(phys_ddr_overall_compat, struct core_mmu_phys_mem) 258 259 #define phys_sdp_mem_begin \ 260 SCATTERED_ARRAY_BEGIN(phys_sdp_mem, struct core_mmu_phys_mem) 261 262 #define phys_sdp_mem_end \ 263 SCATTERED_ARRAY_END(phys_sdp_mem, struct core_mmu_phys_mem) 264 265 #define phys_mem_map_begin \ 266 SCATTERED_ARRAY_BEGIN(phys_mem_map, struct core_mmu_phys_mem) 267 268 #define phys_mem_map_end \ 269 SCATTERED_ARRAY_END(phys_mem_map, struct core_mmu_phys_mem) 270 271 #ifdef CFG_CORE_RESERVED_SHM 272 /* Default NSec shared memory allocated from NSec world */ 273 extern unsigned long default_nsec_shm_paddr; 274 extern unsigned long default_nsec_shm_size; 275 #endif 276 277 void core_init_mmu_map(unsigned long seed, struct core_mmu_config *cfg); 278 void core_init_mmu_regs(struct core_mmu_config *cfg); 279 280 /* Arch specific function to help optimizing 1 MMU xlat table */ 281 bool core_mmu_prefer_tee_ram_at_top(paddr_t paddr); 282 283 /* 284 * struct mmu_partition - stores MMU partition. 285 * 286 * Basically it represent whole MMU mapping. It is possible 287 * to create multiple partitions, and change them in runtime, 288 * effectively changing how OP-TEE sees memory. 289 * This is opaque struct which is defined differently for 290 * v7 and LPAE MMUs 291 * 292 * This structure used mostly when virtualization is enabled. 293 * When CFG_NS_VIRTUALIZATION==n only default partition exists. 294 */ 295 struct mmu_partition; 296 297 /* 298 * core_mmu_get_user_va_range() - Return range of user va space 299 * @base: Lowest user virtual address 300 * @size: Size in bytes of user address space 301 */ 302 void core_mmu_get_user_va_range(vaddr_t *base, size_t *size); 303 304 /* 305 * enum core_mmu_fault - different kinds of faults 306 * @CORE_MMU_FAULT_ALIGNMENT: alignment fault 307 * @CORE_MMU_FAULT_DEBUG_EVENT: debug event 308 * @CORE_MMU_FAULT_TRANSLATION: translation fault 309 * @CORE_MMU_FAULT_WRITE_PERMISSION: Permission fault during write 310 * @CORE_MMU_FAULT_READ_PERMISSION: Permission fault during read 311 * @CORE_MMU_FAULT_ASYNC_EXTERNAL: asynchronous external abort 312 * @CORE_MMU_FAULT_ACCESS_BIT: access bit fault 313 * @CORE_MMU_FAULT_TAG_CHECK: tag check fault 314 * @CORE_MMU_FAULT_OTHER: Other/unknown fault 315 */ 316 enum core_mmu_fault { 317 CORE_MMU_FAULT_ALIGNMENT, 318 CORE_MMU_FAULT_DEBUG_EVENT, 319 CORE_MMU_FAULT_TRANSLATION, 320 CORE_MMU_FAULT_WRITE_PERMISSION, 321 CORE_MMU_FAULT_READ_PERMISSION, 322 CORE_MMU_FAULT_ASYNC_EXTERNAL, 323 CORE_MMU_FAULT_ACCESS_BIT, 324 CORE_MMU_FAULT_TAG_CHECK, 325 CORE_MMU_FAULT_OTHER, 326 }; 327 328 /* 329 * core_mmu_get_fault_type() - get fault type 330 * @fault_descr: Content of fault status or exception syndrome register 331 * @returns an enum describing the content of fault status register. 332 */ 333 enum core_mmu_fault core_mmu_get_fault_type(uint32_t fault_descr); 334 335 /* 336 * core_mm_type_to_attr() - convert memory type to attribute 337 * @t: memory type 338 * @returns an attribute that can be passed to core_mm_set_entry() and friends 339 */ 340 uint32_t core_mmu_type_to_attr(enum teecore_memtypes t); 341 342 /* 343 * core_mmu_create_user_map() - Create user mode mapping 344 * @uctx: Pointer to user mode context 345 * @map: MMU configuration to use when activating this VA space 346 */ 347 void core_mmu_create_user_map(struct user_mode_ctx *uctx, 348 struct core_mmu_user_map *map); 349 /* 350 * core_mmu_get_user_map() - Reads current MMU configuration for user VA space 351 * @map: MMU configuration for current user VA space. 352 */ 353 void core_mmu_get_user_map(struct core_mmu_user_map *map); 354 355 /* 356 * core_mmu_set_user_map() - Set new MMU configuration for user VA space 357 * @map: User context MMU configuration or NULL to set core VA space 358 * 359 * Activate user VA space mapping and set its ASID if @map is not NULL, 360 * otherwise activate core mapping and set ASID to 0. 361 */ 362 void core_mmu_set_user_map(struct core_mmu_user_map *map); 363 364 /* 365 * struct core_mmu_table_info - Properties for a translation table 366 * @table: Pointer to translation table 367 * @va_base: VA base address of the transaltion table 368 * @level: Translation table level 369 * @shift: The shift of each entry in the table 370 * @num_entries: Number of entries in this table. 371 */ 372 struct core_mmu_table_info { 373 void *table; 374 vaddr_t va_base; 375 unsigned level; 376 unsigned shift; 377 unsigned num_entries; 378 #ifdef CFG_NS_VIRTUALIZATION 379 struct mmu_partition *prtn; 380 #endif 381 }; 382 383 /* 384 * core_mmu_find_table() - Locates a translation table 385 * @prtn: MMU partition where search should be performed 386 * @va: Virtual address for the table to cover 387 * @max_level: Don't traverse beyond this level 388 * @tbl_info: Pointer to where to store properties. 389 * @return true if a translation table was found, false on error 390 */ 391 bool core_mmu_find_table(struct mmu_partition *prtn, vaddr_t va, 392 unsigned max_level, 393 struct core_mmu_table_info *tbl_info); 394 395 /* 396 * core_mmu_entry_to_finer_grained() - divide mapping at current level into 397 * smaller ones so memory can be mapped with finer granularity 398 * @tbl_info: table where target record located 399 * @idx: index of record for which a pdgir must be setup. 400 * @secure: true/false if pgdir maps secure/non-secure memory (32bit mmu) 401 * @return true on successful, false on error 402 */ 403 bool core_mmu_entry_to_finer_grained(struct core_mmu_table_info *tbl_info, 404 unsigned int idx, bool secure); 405 406 void core_mmu_set_entry_primitive(void *table, size_t level, size_t idx, 407 paddr_t pa, uint32_t attr); 408 409 void core_mmu_get_user_pgdir(struct core_mmu_table_info *pgd_info); 410 411 /* 412 * core_mmu_set_entry() - Set entry in translation table 413 * @tbl_info: Translation table properties 414 * @idx: Index of entry to update 415 * @pa: Physical address to assign entry 416 * @attr: Attributes to assign entry 417 */ 418 void core_mmu_set_entry(struct core_mmu_table_info *tbl_info, unsigned idx, 419 paddr_t pa, uint32_t attr); 420 421 void core_mmu_get_entry_primitive(const void *table, size_t level, size_t idx, 422 paddr_t *pa, uint32_t *attr); 423 424 /* 425 * core_mmu_get_entry() - Get entry from translation table 426 * @tbl_info: Translation table properties 427 * @idx: Index of entry to read 428 * @pa: Physical address is returned here if pa is not NULL 429 * @attr: Attributues are returned here if attr is not NULL 430 */ 431 void core_mmu_get_entry(struct core_mmu_table_info *tbl_info, unsigned idx, 432 paddr_t *pa, uint32_t *attr); 433 434 /* 435 * core_mmu_va2idx() - Translate from virtual address to table index 436 * @tbl_info: Translation table properties 437 * @va: Virtual address to translate 438 * @returns index in transaltion table 439 */ 440 static inline unsigned core_mmu_va2idx(struct core_mmu_table_info *tbl_info, 441 vaddr_t va) 442 { 443 return (va - tbl_info->va_base) >> tbl_info->shift; 444 } 445 446 /* 447 * core_mmu_idx2va() - Translate from table index to virtual address 448 * @tbl_info: Translation table properties 449 * @idx: Index to translate 450 * @returns Virtual address 451 */ 452 static inline vaddr_t core_mmu_idx2va(struct core_mmu_table_info *tbl_info, 453 unsigned idx) 454 { 455 return (idx << tbl_info->shift) + tbl_info->va_base; 456 } 457 458 /* 459 * core_mmu_get_block_offset() - Get offset inside a block/page 460 * @tbl_info: Translation table properties 461 * @pa: Physical address 462 * @returns offset within one block of the translation table 463 */ 464 static inline size_t core_mmu_get_block_offset( 465 struct core_mmu_table_info *tbl_info, paddr_t pa) 466 { 467 return pa & ((1 << tbl_info->shift) - 1); 468 } 469 470 /* 471 * core_mmu_is_dynamic_vaspace() - Check if memory region belongs to 472 * empty virtual address space that is used for dymanic mappings 473 * @mm: memory region to be checked 474 * @returns result of the check 475 */ 476 static inline bool core_mmu_is_dynamic_vaspace(struct tee_mmap_region *mm) 477 { 478 return mm->type == MEM_AREA_RES_VASPACE || 479 mm->type == MEM_AREA_SHM_VASPACE; 480 } 481 482 /* 483 * core_mmu_map_pages() - map list of pages at given virtual address 484 * @vstart: Virtual address where mapping begins 485 * @pages: Array of page addresses 486 * @num_pages: Number of pages 487 * @memtype: Type of memmory to be mapped 488 * 489 * Note: This function asserts that pages are not mapped executeable for 490 * kernel (privileged) mode. 491 * 492 * @returns: TEE_SUCCESS on success, TEE_ERROR_XXX on error 493 */ 494 TEE_Result core_mmu_map_pages(vaddr_t vstart, paddr_t *pages, size_t num_pages, 495 enum teecore_memtypes memtype); 496 497 /* 498 * core_mmu_map_contiguous_pages() - map range of pages at given virtual address 499 * @vstart: Virtual address where mapping begins 500 * @pstart: Physical address of the first page 501 * @num_pages: Number of pages 502 * @memtype: Type of memmory to be mapped 503 * 504 * Note: This function asserts that pages are not mapped executeable for 505 * kernel (privileged) mode. 506 * 507 * @returns: TEE_SUCCESS on success, TEE_ERROR_XXX on error 508 */ 509 TEE_Result core_mmu_map_contiguous_pages(vaddr_t vstart, paddr_t pstart, 510 size_t num_pages, 511 enum teecore_memtypes memtype); 512 513 /* 514 * core_mmu_unmap_pages() - remove mapping at given virtual address 515 * @vstart: Virtual address where mapping begins 516 * @num_pages: Number of pages to unmap 517 */ 518 void core_mmu_unmap_pages(vaddr_t vstart, size_t num_pages); 519 520 /* 521 * core_mmu_user_mapping_is_active() - Report if user mapping is active 522 * @returns true if a user VA space is active, false if user VA space is 523 * inactive. 524 */ 525 bool core_mmu_user_mapping_is_active(void); 526 527 /* 528 * core_mmu_mattr_is_ok() - Check that supplied mem attributes can be used 529 * @returns true if the attributes can be used, false if not. 530 */ 531 bool core_mmu_mattr_is_ok(uint32_t mattr); 532 533 void core_mmu_get_mem_by_type(enum teecore_memtypes type, vaddr_t *s, 534 vaddr_t *e); 535 536 enum teecore_memtypes core_mmu_get_type_by_pa(paddr_t pa); 537 538 /* routines to retreive shared mem configuration */ 539 static inline bool core_mmu_is_shm_cached(void) 540 { 541 return mattr_is_cached(core_mmu_type_to_attr(MEM_AREA_NSEC_SHM)); 542 } 543 544 TEE_Result core_mmu_remove_mapping(enum teecore_memtypes type, void *addr, 545 size_t len); 546 void *core_mmu_add_mapping(enum teecore_memtypes type, paddr_t addr, 547 size_t len); 548 549 /* 550 * core_mmu_find_mapping_exclusive() - Find mapping of specified type and 551 * length. If more than one mapping of 552 * specified type is present, NULL will be 553 * returned. 554 * @type: memory type 555 * @len: length in bytes 556 */ 557 struct tee_mmap_region * 558 core_mmu_find_mapping_exclusive(enum teecore_memtypes type, size_t len); 559 560 /* 561 * tlbi_mva_range() - Invalidate TLB for virtual address range 562 * @va: start virtual address, must be a multiple of @granule 563 * @len: length in bytes of range, must be a multiple of @granule 564 * @granule: granularity of mapping, supported values are 565 * CORE_MMU_PGDIR_SIZE or SMALL_PAGE_SIZE. This value must 566 * match the actual mappings. 567 */ 568 void tlbi_mva_range(vaddr_t va, size_t len, size_t granule); 569 570 /* 571 * tlbi_mva_range_asid() - Invalidate TLB for virtual address range for 572 * a specific ASID 573 * @va: start virtual address, must be a multiple of @granule 574 * @len: length in bytes of range, must be a multiple of @granule 575 * @granule: granularity of mapping, supported values are 576 * CORE_MMU_PGDIR_SIZE or SMALL_PAGE_SIZE. This value must 577 * match the actual mappings. 578 * @asid: Address space identifier 579 */ 580 void tlbi_mva_range_asid(vaddr_t va, size_t len, size_t granule, uint32_t asid); 581 582 /* Check cpu mmu enabled or not */ 583 bool cpu_mmu_enabled(void); 584 585 #ifdef CFG_CORE_DYN_SHM 586 /* 587 * Check if platform defines nsec DDR range(s). 588 * Static SHM (MEM_AREA_NSEC_SHM) is not covered by this API as it is 589 * always present. 590 */ 591 bool core_mmu_nsec_ddr_is_defined(void); 592 593 void core_mmu_set_discovered_nsec_ddr(struct core_mmu_phys_mem *start, 594 size_t nelems); 595 #endif 596 597 /* Initialize MMU partition */ 598 void core_init_mmu_prtn(struct mmu_partition *prtn, struct tee_mmap_region *mm); 599 600 unsigned int asid_alloc(void); 601 void asid_free(unsigned int asid); 602 603 #ifdef CFG_SECURE_DATA_PATH 604 /* Alloc and fill SDP memory objects table - table is NULL terminated */ 605 struct mobj **core_sdp_mem_create_mobjs(void); 606 #endif 607 608 #ifdef CFG_NS_VIRTUALIZATION 609 size_t core_mmu_get_total_pages_size(void); 610 struct mmu_partition *core_alloc_mmu_prtn(void *tables); 611 void core_free_mmu_prtn(struct mmu_partition *prtn); 612 void core_mmu_set_prtn(struct mmu_partition *prtn); 613 void core_mmu_set_default_prtn(void); 614 void core_mmu_set_default_prtn_tbl(void); 615 #endif 616 617 void core_mmu_init_virtualization(void); 618 619 /* init some allocation pools */ 620 void core_mmu_init_ta_ram(void); 621 622 void core_init_mmu(struct tee_mmap_region *mm); 623 624 void core_mmu_set_info_table(struct core_mmu_table_info *tbl_info, 625 unsigned int level, vaddr_t va_base, void *table); 626 void core_mmu_populate_user_map(struct core_mmu_table_info *dir_info, 627 struct user_mode_ctx *uctx); 628 void core_mmu_map_region(struct mmu_partition *prtn, 629 struct tee_mmap_region *mm); 630 631 bool arch_va2pa_helper(void *va, paddr_t *pa); 632 633 static inline bool core_mmap_is_end_of_table(const struct tee_mmap_region *mm) 634 { 635 return mm->type == MEM_AREA_END; 636 } 637 638 static inline bool core_mmu_check_end_pa(paddr_t pa, size_t len) 639 { 640 paddr_t end_pa = 0; 641 642 if (ADD_OVERFLOW(pa, len - 1, &end_pa)) 643 return false; 644 return core_mmu_check_max_pa(end_pa); 645 } 646 #endif /*__ASSEMBLER__*/ 647 648 #endif /* CORE_MMU_H */ 649