1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 #ifndef CORE_MMU_H 7 #define CORE_MMU_H 8 9 #ifndef __ASSEMBLER__ 10 #include <assert.h> 11 #include <compiler.h> 12 #include <kernel/user_ta.h> 13 #include <mm/tee_mmu_types.h> 14 #include <types_ext.h> 15 #include <util.h> 16 #endif 17 18 #include <mm/core_mmu_arch.h> 19 #include <platform_config.h> 20 21 /* A small page is the smallest unit of memory that can be mapped */ 22 #define SMALL_PAGE_SIZE BIT(SMALL_PAGE_SHIFT) 23 #define SMALL_PAGE_MASK ((paddr_t)SMALL_PAGE_SIZE - 1) 24 25 /* 26 * PGDIR is the translation table above the translation table that holds 27 * the pages. 28 */ 29 #define CORE_MMU_PGDIR_SIZE BIT(CORE_MMU_PGDIR_SHIFT) 30 #define CORE_MMU_PGDIR_MASK ((paddr_t)CORE_MMU_PGDIR_SIZE - 1) 31 32 /* TA user space code, data, stack and heap are mapped using this granularity */ 33 #define CORE_MMU_USER_CODE_SIZE BIT(CORE_MMU_USER_CODE_SHIFT) 34 #define CORE_MMU_USER_CODE_MASK ((paddr_t)CORE_MMU_USER_CODE_SIZE - 1) 35 36 /* TA user space parameters are mapped using this granularity */ 37 #define CORE_MMU_USER_PARAM_SIZE BIT(CORE_MMU_USER_PARAM_SHIFT) 38 #define CORE_MMU_USER_PARAM_MASK ((paddr_t)CORE_MMU_USER_PARAM_SIZE - 1) 39 40 /* 41 * Identify mapping constraint: virtual base address is the physical start addr. 42 * If platform did not set some macros, some get default value. 43 */ 44 #ifndef TEE_RAM_VA_SIZE 45 #define TEE_RAM_VA_SIZE CORE_MMU_PGDIR_SIZE 46 #endif 47 48 #ifndef TEE_LOAD_ADDR 49 #define TEE_LOAD_ADDR TEE_RAM_START 50 #endif 51 52 #ifndef STACK_ALIGNMENT 53 #define STACK_ALIGNMENT (sizeof(long) * U(2)) 54 #endif 55 56 #ifndef __ASSEMBLER__ 57 /* 58 * Memory area type: 59 * MEM_AREA_END: Reserved, marks the end of a table of mapping areas. 60 * MEM_AREA_TEE_RAM: core RAM (read/write/executable, secure, reserved to TEE) 61 * MEM_AREA_TEE_RAM_RX: core private read-only/executable memory (secure) 62 * MEM_AREA_TEE_RAM_RO: core private read-only/non-executable memory (secure) 63 * MEM_AREA_TEE_RAM_RW: core private read/write/non-executable memory (secure) 64 * MEM_AREA_INIT_RAM_RO: init private read-only/non-executable memory (secure) 65 * MEM_AREA_INIT_RAM_RX: init private read-only/executable memory (secure) 66 * MEM_AREA_NEX_RAM_RO: nexus private read-only/non-executable memory (secure) 67 * MEM_AREA_NEX_RAM_RW: nexus private r/w/non-executable memory (secure) 68 * MEM_AREA_TEE_COHERENT: teecore coherent RAM (secure, reserved to TEE) 69 * MEM_AREA_TEE_ASAN: core address sanitizer RAM (secure, reserved to TEE) 70 * MEM_AREA_IDENTITY_MAP_RX: core identity mapped r/o executable memory (secure) 71 * MEM_AREA_TA_RAM: Secure RAM where teecore loads/exec TA instances. 72 * MEM_AREA_NSEC_SHM: NonSecure shared RAM between NSec and TEE. 73 * MEM_AREA_NEX_NSEC_SHM: nexus non-secure shared RAM between NSec and TEE. 74 * MEM_AREA_RAM_NSEC: NonSecure RAM storing data 75 * MEM_AREA_RAM_SEC: Secure RAM storing some secrets 76 * MEM_AREA_IO_NSEC: NonSecure HW mapped registers 77 * MEM_AREA_IO_SEC: Secure HW mapped registers 78 * MEM_AREA_EXT_DT: Memory loads external device tree 79 * MEM_AREA_RES_VASPACE: Reserved virtual memory space 80 * MEM_AREA_SHM_VASPACE: Virtual memory space for dynamic shared memory buffers 81 * MEM_AREA_TS_VASPACE: TS va space, only used with phys_to_virt() 82 * MEM_AREA_DDR_OVERALL: Overall DDR address range, candidate to dynamic shm. 83 * MEM_AREA_SEC_RAM_OVERALL: Whole secure RAM 84 * MEM_AREA_MAXTYPE: lower invalid 'type' value 85 */ 86 enum teecore_memtypes { 87 MEM_AREA_END = 0, 88 MEM_AREA_TEE_RAM, 89 MEM_AREA_TEE_RAM_RX, 90 MEM_AREA_TEE_RAM_RO, 91 MEM_AREA_TEE_RAM_RW, 92 MEM_AREA_INIT_RAM_RO, 93 MEM_AREA_INIT_RAM_RX, 94 MEM_AREA_NEX_RAM_RO, 95 MEM_AREA_NEX_RAM_RW, 96 MEM_AREA_TEE_COHERENT, 97 MEM_AREA_TEE_ASAN, 98 MEM_AREA_IDENTITY_MAP_RX, 99 MEM_AREA_TA_RAM, 100 MEM_AREA_NSEC_SHM, 101 MEM_AREA_NEX_NSEC_SHM, 102 MEM_AREA_RAM_NSEC, 103 MEM_AREA_RAM_SEC, 104 MEM_AREA_IO_NSEC, 105 MEM_AREA_IO_SEC, 106 MEM_AREA_EXT_DT, 107 MEM_AREA_RES_VASPACE, 108 MEM_AREA_SHM_VASPACE, 109 MEM_AREA_TS_VASPACE, 110 MEM_AREA_PAGER_VASPACE, 111 MEM_AREA_SDP_MEM, 112 MEM_AREA_DDR_OVERALL, 113 MEM_AREA_SEC_RAM_OVERALL, 114 MEM_AREA_MAXTYPE 115 }; 116 117 static inline const char *teecore_memtype_name(enum teecore_memtypes type) 118 { 119 static const char * const names[] = { 120 [MEM_AREA_END] = "END", 121 [MEM_AREA_TEE_RAM] = "TEE_RAM_RWX", 122 [MEM_AREA_TEE_RAM_RX] = "TEE_RAM_RX", 123 [MEM_AREA_TEE_RAM_RO] = "TEE_RAM_RO", 124 [MEM_AREA_TEE_RAM_RW] = "TEE_RAM_RW", 125 [MEM_AREA_INIT_RAM_RO] = "INIT_RAM_RO", 126 [MEM_AREA_INIT_RAM_RX] = "INIT_RAM_RX", 127 [MEM_AREA_NEX_RAM_RO] = "NEX_RAM_RO", 128 [MEM_AREA_NEX_RAM_RW] = "NEX_RAM_RW", 129 [MEM_AREA_TEE_ASAN] = "TEE_ASAN", 130 [MEM_AREA_IDENTITY_MAP_RX] = "IDENTITY_MAP_RX", 131 [MEM_AREA_TEE_COHERENT] = "TEE_COHERENT", 132 [MEM_AREA_TA_RAM] = "TA_RAM", 133 [MEM_AREA_NSEC_SHM] = "NSEC_SHM", 134 [MEM_AREA_NEX_NSEC_SHM] = "NEX_NSEC_SHM", 135 [MEM_AREA_RAM_NSEC] = "RAM_NSEC", 136 [MEM_AREA_RAM_SEC] = "RAM_SEC", 137 [MEM_AREA_IO_NSEC] = "IO_NSEC", 138 [MEM_AREA_IO_SEC] = "IO_SEC", 139 [MEM_AREA_EXT_DT] = "EXT_DT", 140 [MEM_AREA_RES_VASPACE] = "RES_VASPACE", 141 [MEM_AREA_SHM_VASPACE] = "SHM_VASPACE", 142 [MEM_AREA_TS_VASPACE] = "TS_VASPACE", 143 [MEM_AREA_PAGER_VASPACE] = "PAGER_VASPACE", 144 [MEM_AREA_SDP_MEM] = "SDP_MEM", 145 [MEM_AREA_DDR_OVERALL] = "DDR_OVERALL", 146 [MEM_AREA_SEC_RAM_OVERALL] = "SEC_RAM_OVERALL", 147 }; 148 149 COMPILE_TIME_ASSERT(ARRAY_SIZE(names) == MEM_AREA_MAXTYPE); 150 return names[type]; 151 } 152 153 #ifdef CFG_CORE_RWDATA_NOEXEC 154 #define MEM_AREA_TEE_RAM_RW_DATA MEM_AREA_TEE_RAM_RW 155 #else 156 #define MEM_AREA_TEE_RAM_RW_DATA MEM_AREA_TEE_RAM 157 #endif 158 159 struct core_mmu_phys_mem { 160 const char *name; 161 enum teecore_memtypes type; 162 __extension__ union { 163 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 164 struct { 165 uint32_t lo_addr; 166 uint32_t hi_addr; 167 }; 168 #endif 169 paddr_t addr; 170 }; 171 __extension__ union { 172 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 173 struct { 174 uint32_t lo_size; 175 uint32_t hi_size; 176 }; 177 #endif 178 paddr_size_t size; 179 }; 180 }; 181 182 #define __register_memory(_name, _type, _addr, _size, _section) \ 183 SCATTERED_ARRAY_DEFINE_ITEM(_section, struct core_mmu_phys_mem) = \ 184 { .name = (_name), .type = (_type), .addr = (_addr), \ 185 .size = (_size) } 186 187 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 188 #define __register_memory_ul(_name, _type, _addr, _size, _section) \ 189 SCATTERED_ARRAY_DEFINE_ITEM(_section, struct core_mmu_phys_mem) = \ 190 { .name = (_name), .type = (_type), .lo_addr = (_addr), \ 191 .lo_size = (_size) } 192 #else 193 #define __register_memory_ul(_name, _type, _addr, _size, _section) \ 194 __register_memory(_name, _type, _addr, _size, _section) 195 #endif 196 197 #define register_phys_mem(type, addr, size) \ 198 __register_memory(#addr, (type), (addr), (size), \ 199 phys_mem_map) 200 201 #define register_phys_mem_ul(type, addr, size) \ 202 __register_memory_ul(#addr, (type), (addr), (size), \ 203 phys_mem_map) 204 205 /* Same as register_phys_mem() but with PGDIR_SIZE granularity */ 206 #define register_phys_mem_pgdir(type, addr, size) \ 207 __register_memory(#addr, type, ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \ 208 ROUNDUP(size + addr - \ 209 ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \ 210 CORE_MMU_PGDIR_SIZE), phys_mem_map) 211 212 #ifdef CFG_SECURE_DATA_PATH 213 #define register_sdp_mem(addr, size) \ 214 __register_memory(#addr, MEM_AREA_SDP_MEM, (addr), (size), \ 215 phys_sdp_mem) 216 #else 217 #define register_sdp_mem(addr, size) \ 218 static int CONCAT(__register_sdp_mem_unused, __COUNTER__) \ 219 __unused 220 #endif 221 222 /* register_dynamic_shm() is deprecated, please use register_ddr() instead */ 223 #define register_dynamic_shm(addr, size) \ 224 __register_memory(#addr, MEM_AREA_DDR_OVERALL, (addr), (size), \ 225 phys_ddr_overall_compat) 226 227 /* 228 * register_ddr() - Define a memory range 229 * @addr: Base address 230 * @size: Length 231 * 232 * This macro can be used multiple times to define disjoint ranges. While 233 * initializing holes are carved out of these ranges where it overlaps with 234 * special memory, for instance memory registered with register_sdp_mem(). 235 * 236 * The memory that remains is accepted as non-secure shared memory when 237 * communicating with normal world. 238 * 239 * This macro is an alternative to supply the memory description with a 240 * devicetree blob. 241 */ 242 #define register_ddr(addr, size) \ 243 __register_memory(#addr, MEM_AREA_DDR_OVERALL, (addr), \ 244 (size), phys_ddr_overall) 245 246 #define phys_ddr_overall_begin \ 247 SCATTERED_ARRAY_BEGIN(phys_ddr_overall, struct core_mmu_phys_mem) 248 249 #define phys_ddr_overall_end \ 250 SCATTERED_ARRAY_END(phys_ddr_overall, struct core_mmu_phys_mem) 251 252 #define phys_ddr_overall_compat_begin \ 253 SCATTERED_ARRAY_BEGIN(phys_ddr_overall_compat, struct core_mmu_phys_mem) 254 255 #define phys_ddr_overall_compat_end \ 256 SCATTERED_ARRAY_END(phys_ddr_overall_compat, struct core_mmu_phys_mem) 257 258 #define phys_sdp_mem_begin \ 259 SCATTERED_ARRAY_BEGIN(phys_sdp_mem, struct core_mmu_phys_mem) 260 261 #define phys_sdp_mem_end \ 262 SCATTERED_ARRAY_END(phys_sdp_mem, struct core_mmu_phys_mem) 263 264 #define phys_mem_map_begin \ 265 SCATTERED_ARRAY_BEGIN(phys_mem_map, struct core_mmu_phys_mem) 266 267 #define phys_mem_map_end \ 268 SCATTERED_ARRAY_END(phys_mem_map, struct core_mmu_phys_mem) 269 270 #ifdef CFG_CORE_RESERVED_SHM 271 /* Default NSec shared memory allocated from NSec world */ 272 extern unsigned long default_nsec_shm_paddr; 273 extern unsigned long default_nsec_shm_size; 274 #endif 275 276 /* 277 * Physical load address of OP-TEE updated during boot if needed to reflect 278 * the value used. 279 */ 280 #ifdef CFG_CORE_PHYS_RELOCATABLE 281 extern unsigned long core_mmu_tee_load_pa; 282 #else 283 extern const unsigned long core_mmu_tee_load_pa; 284 #endif 285 286 void core_init_mmu_map(unsigned long seed, struct core_mmu_config *cfg); 287 void core_init_mmu_regs(struct core_mmu_config *cfg); 288 289 /* Arch specific function to help optimizing 1 MMU xlat table */ 290 bool core_mmu_prefer_tee_ram_at_top(paddr_t paddr); 291 292 /* 293 * struct mmu_partition - stores MMU partition. 294 * 295 * Basically it represent whole MMU mapping. It is possible 296 * to create multiple partitions, and change them in runtime, 297 * effectively changing how OP-TEE sees memory. 298 * This is opaque struct which is defined differently for 299 * v7 and LPAE MMUs 300 * 301 * This structure used mostly when virtualization is enabled. 302 * When CFG_NS_VIRTUALIZATION==n only default partition exists. 303 */ 304 struct mmu_partition; 305 306 /* 307 * core_mmu_get_user_va_range() - Return range of user va space 308 * @base: Lowest user virtual address 309 * @size: Size in bytes of user address space 310 */ 311 void core_mmu_get_user_va_range(vaddr_t *base, size_t *size); 312 313 /* 314 * enum core_mmu_fault - different kinds of faults 315 * @CORE_MMU_FAULT_ALIGNMENT: alignment fault 316 * @CORE_MMU_FAULT_DEBUG_EVENT: debug event 317 * @CORE_MMU_FAULT_TRANSLATION: translation fault 318 * @CORE_MMU_FAULT_WRITE_PERMISSION: Permission fault during write 319 * @CORE_MMU_FAULT_READ_PERMISSION: Permission fault during read 320 * @CORE_MMU_FAULT_ASYNC_EXTERNAL: asynchronous external abort 321 * @CORE_MMU_FAULT_ACCESS_BIT: access bit fault 322 * @CORE_MMU_FAULT_TAG_CHECK: tag check fault 323 * @CORE_MMU_FAULT_OTHER: Other/unknown fault 324 */ 325 enum core_mmu_fault { 326 CORE_MMU_FAULT_ALIGNMENT, 327 CORE_MMU_FAULT_DEBUG_EVENT, 328 CORE_MMU_FAULT_TRANSLATION, 329 CORE_MMU_FAULT_WRITE_PERMISSION, 330 CORE_MMU_FAULT_READ_PERMISSION, 331 CORE_MMU_FAULT_ASYNC_EXTERNAL, 332 CORE_MMU_FAULT_ACCESS_BIT, 333 CORE_MMU_FAULT_TAG_CHECK, 334 CORE_MMU_FAULT_OTHER, 335 }; 336 337 /* 338 * core_mmu_get_fault_type() - get fault type 339 * @fault_descr: Content of fault status or exception syndrome register 340 * @returns an enum describing the content of fault status register. 341 */ 342 enum core_mmu_fault core_mmu_get_fault_type(uint32_t fault_descr); 343 344 /* 345 * core_mm_type_to_attr() - convert memory type to attribute 346 * @t: memory type 347 * @returns an attribute that can be passed to core_mm_set_entry() and friends 348 */ 349 uint32_t core_mmu_type_to_attr(enum teecore_memtypes t); 350 351 /* 352 * core_mmu_create_user_map() - Create user mode mapping 353 * @uctx: Pointer to user mode context 354 * @map: MMU configuration to use when activating this VA space 355 */ 356 void core_mmu_create_user_map(struct user_mode_ctx *uctx, 357 struct core_mmu_user_map *map); 358 /* 359 * core_mmu_get_user_map() - Reads current MMU configuration for user VA space 360 * @map: MMU configuration for current user VA space. 361 */ 362 void core_mmu_get_user_map(struct core_mmu_user_map *map); 363 364 /* 365 * core_mmu_set_user_map() - Set new MMU configuration for user VA space 366 * @map: User context MMU configuration or NULL to set core VA space 367 * 368 * Activate user VA space mapping and set its ASID if @map is not NULL, 369 * otherwise activate core mapping and set ASID to 0. 370 */ 371 void core_mmu_set_user_map(struct core_mmu_user_map *map); 372 373 /* 374 * struct core_mmu_table_info - Properties for a translation table 375 * @table: Pointer to translation table 376 * @va_base: VA base address of the transaltion table 377 * @level: Translation table level 378 * @next_level: Finer grained translation table level according to @level. 379 * @shift: The shift of each entry in the table 380 * @num_entries: Number of entries in this table. 381 */ 382 struct core_mmu_table_info { 383 void *table; 384 vaddr_t va_base; 385 unsigned num_entries; 386 #ifdef CFG_NS_VIRTUALIZATION 387 struct mmu_partition *prtn; 388 #endif 389 uint8_t level; 390 uint8_t shift; 391 uint8_t next_level; 392 }; 393 394 /* 395 * core_mmu_find_table() - Locates a translation table 396 * @prtn: MMU partition where search should be performed 397 * @va: Virtual address for the table to cover 398 * @max_level: Don't traverse beyond this level 399 * @tbl_info: Pointer to where to store properties. 400 * @return true if a translation table was found, false on error 401 */ 402 bool core_mmu_find_table(struct mmu_partition *prtn, vaddr_t va, 403 unsigned max_level, 404 struct core_mmu_table_info *tbl_info); 405 406 /* 407 * core_mmu_entry_to_finer_grained() - divide mapping at current level into 408 * smaller ones so memory can be mapped with finer granularity 409 * @tbl_info: table where target record located 410 * @idx: index of record for which a pdgir must be setup. 411 * @secure: true/false if pgdir maps secure/non-secure memory (32bit mmu) 412 * @return true on successful, false on error 413 */ 414 bool core_mmu_entry_to_finer_grained(struct core_mmu_table_info *tbl_info, 415 unsigned int idx, bool secure); 416 417 void core_mmu_set_entry_primitive(void *table, size_t level, size_t idx, 418 paddr_t pa, uint32_t attr); 419 420 void core_mmu_get_user_pgdir(struct core_mmu_table_info *pgd_info); 421 422 /* 423 * core_mmu_set_entry() - Set entry in translation table 424 * @tbl_info: Translation table properties 425 * @idx: Index of entry to update 426 * @pa: Physical address to assign entry 427 * @attr: Attributes to assign entry 428 */ 429 void core_mmu_set_entry(struct core_mmu_table_info *tbl_info, unsigned idx, 430 paddr_t pa, uint32_t attr); 431 432 void core_mmu_get_entry_primitive(const void *table, size_t level, size_t idx, 433 paddr_t *pa, uint32_t *attr); 434 435 /* 436 * core_mmu_get_entry() - Get entry from translation table 437 * @tbl_info: Translation table properties 438 * @idx: Index of entry to read 439 * @pa: Physical address is returned here if pa is not NULL 440 * @attr: Attributues are returned here if attr is not NULL 441 */ 442 void core_mmu_get_entry(struct core_mmu_table_info *tbl_info, unsigned idx, 443 paddr_t *pa, uint32_t *attr); 444 445 /* 446 * core_mmu_va2idx() - Translate from virtual address to table index 447 * @tbl_info: Translation table properties 448 * @va: Virtual address to translate 449 * @returns index in transaltion table 450 */ 451 static inline unsigned core_mmu_va2idx(struct core_mmu_table_info *tbl_info, 452 vaddr_t va) 453 { 454 return (va - tbl_info->va_base) >> tbl_info->shift; 455 } 456 457 /* 458 * core_mmu_idx2va() - Translate from table index to virtual address 459 * @tbl_info: Translation table properties 460 * @idx: Index to translate 461 * @returns Virtual address 462 */ 463 static inline vaddr_t core_mmu_idx2va(struct core_mmu_table_info *tbl_info, 464 unsigned idx) 465 { 466 return (idx << tbl_info->shift) + tbl_info->va_base; 467 } 468 469 /* 470 * core_mmu_get_block_offset() - Get offset inside a block/page 471 * @tbl_info: Translation table properties 472 * @pa: Physical address 473 * @returns offset within one block of the translation table 474 */ 475 static inline size_t core_mmu_get_block_offset( 476 struct core_mmu_table_info *tbl_info, paddr_t pa) 477 { 478 return pa & ((1 << tbl_info->shift) - 1); 479 } 480 481 /* 482 * core_mmu_is_dynamic_vaspace() - Check if memory region belongs to 483 * empty virtual address space that is used for dymanic mappings 484 * @mm: memory region to be checked 485 * @returns result of the check 486 */ 487 static inline bool core_mmu_is_dynamic_vaspace(struct tee_mmap_region *mm) 488 { 489 return mm->type == MEM_AREA_RES_VASPACE || 490 mm->type == MEM_AREA_SHM_VASPACE; 491 } 492 493 /* 494 * core_mmu_map_pages() - map list of pages at given virtual address 495 * @vstart: Virtual address where mapping begins 496 * @pages: Array of page addresses 497 * @num_pages: Number of pages 498 * @memtype: Type of memmory to be mapped 499 * 500 * Note: This function asserts that pages are not mapped executeable for 501 * kernel (privileged) mode. 502 * 503 * @returns: TEE_SUCCESS on success, TEE_ERROR_XXX on error 504 */ 505 TEE_Result core_mmu_map_pages(vaddr_t vstart, paddr_t *pages, size_t num_pages, 506 enum teecore_memtypes memtype); 507 508 /* 509 * core_mmu_map_contiguous_pages() - map range of pages at given virtual address 510 * @vstart: Virtual address where mapping begins 511 * @pstart: Physical address of the first page 512 * @num_pages: Number of pages 513 * @memtype: Type of memmory to be mapped 514 * 515 * Note: This function asserts that pages are not mapped executeable for 516 * kernel (privileged) mode. 517 * 518 * @returns: TEE_SUCCESS on success, TEE_ERROR_XXX on error 519 */ 520 TEE_Result core_mmu_map_contiguous_pages(vaddr_t vstart, paddr_t pstart, 521 size_t num_pages, 522 enum teecore_memtypes memtype); 523 524 /* 525 * core_mmu_unmap_pages() - remove mapping at given virtual address 526 * @vstart: Virtual address where mapping begins 527 * @num_pages: Number of pages to unmap 528 */ 529 void core_mmu_unmap_pages(vaddr_t vstart, size_t num_pages); 530 531 /* 532 * core_mmu_user_mapping_is_active() - Report if user mapping is active 533 * @returns true if a user VA space is active, false if user VA space is 534 * inactive. 535 */ 536 bool core_mmu_user_mapping_is_active(void); 537 538 /* 539 * core_mmu_mattr_is_ok() - Check that supplied mem attributes can be used 540 * @returns true if the attributes can be used, false if not. 541 */ 542 bool core_mmu_mattr_is_ok(uint32_t mattr); 543 544 void core_mmu_get_mem_by_type(enum teecore_memtypes type, vaddr_t *s, 545 vaddr_t *e); 546 547 enum teecore_memtypes core_mmu_get_type_by_pa(paddr_t pa); 548 549 /* routines to retreive shared mem configuration */ 550 static inline bool core_mmu_is_shm_cached(void) 551 { 552 return mattr_is_cached(core_mmu_type_to_attr(MEM_AREA_NSEC_SHM)); 553 } 554 555 TEE_Result core_mmu_remove_mapping(enum teecore_memtypes type, void *addr, 556 size_t len); 557 void *core_mmu_add_mapping(enum teecore_memtypes type, paddr_t addr, 558 size_t len); 559 560 /* 561 * core_mmu_find_mapping_exclusive() - Find mapping of specified type and 562 * length. If more than one mapping of 563 * specified type is present, NULL will be 564 * returned. 565 * @type: memory type 566 * @len: length in bytes 567 */ 568 struct tee_mmap_region * 569 core_mmu_find_mapping_exclusive(enum teecore_memtypes type, size_t len); 570 571 /* 572 * tlbi_va_range() - Invalidate TLB for virtual address range 573 * @va: start virtual address, must be a multiple of @granule 574 * @len: length in bytes of range, must be a multiple of @granule 575 * @granule: granularity of mapping, supported values are 576 * CORE_MMU_PGDIR_SIZE or SMALL_PAGE_SIZE. This value must 577 * match the actual mappings. 578 */ 579 void tlbi_va_range(vaddr_t va, size_t len, size_t granule); 580 581 /* 582 * tlbi_va_range_asid() - Invalidate TLB for virtual address range for 583 * a specific ASID 584 * @va: start virtual address, must be a multiple of @granule 585 * @len: length in bytes of range, must be a multiple of @granule 586 * @granule: granularity of mapping, supported values are 587 * CORE_MMU_PGDIR_SIZE or SMALL_PAGE_SIZE. This value must 588 * match the actual mappings. 589 * @asid: Address space identifier 590 */ 591 void tlbi_va_range_asid(vaddr_t va, size_t len, size_t granule, uint32_t asid); 592 593 /* Check cpu mmu enabled or not */ 594 bool cpu_mmu_enabled(void); 595 596 #ifdef CFG_CORE_DYN_SHM 597 /* 598 * Check if platform defines nsec DDR range(s). 599 * Static SHM (MEM_AREA_NSEC_SHM) is not covered by this API as it is 600 * always present. 601 */ 602 bool core_mmu_nsec_ddr_is_defined(void); 603 604 void core_mmu_set_discovered_nsec_ddr(struct core_mmu_phys_mem *start, 605 size_t nelems); 606 #endif 607 608 /* Initialize MMU partition */ 609 void core_init_mmu_prtn(struct mmu_partition *prtn, struct tee_mmap_region *mm); 610 611 unsigned int asid_alloc(void); 612 void asid_free(unsigned int asid); 613 614 #ifdef CFG_SECURE_DATA_PATH 615 /* Alloc and fill SDP memory objects table - table is NULL terminated */ 616 struct mobj **core_sdp_mem_create_mobjs(void); 617 #endif 618 619 #ifdef CFG_NS_VIRTUALIZATION 620 size_t core_mmu_get_total_pages_size(void); 621 struct mmu_partition *core_alloc_mmu_prtn(void *tables); 622 void core_free_mmu_prtn(struct mmu_partition *prtn); 623 void core_mmu_set_prtn(struct mmu_partition *prtn); 624 void core_mmu_set_default_prtn(void); 625 void core_mmu_set_default_prtn_tbl(void); 626 #endif 627 628 void core_mmu_init_virtualization(void); 629 630 /* init some allocation pools */ 631 void core_mmu_init_ta_ram(void); 632 633 void core_init_mmu(struct tee_mmap_region *mm); 634 635 void core_mmu_set_info_table(struct core_mmu_table_info *tbl_info, 636 unsigned int level, vaddr_t va_base, void *table); 637 void core_mmu_populate_user_map(struct core_mmu_table_info *dir_info, 638 struct user_mode_ctx *uctx); 639 void core_mmu_map_region(struct mmu_partition *prtn, 640 struct tee_mmap_region *mm); 641 642 bool arch_va2pa_helper(void *va, paddr_t *pa); 643 644 static inline bool core_mmap_is_end_of_table(const struct tee_mmap_region *mm) 645 { 646 return mm->type == MEM_AREA_END; 647 } 648 649 static inline bool core_mmu_check_end_pa(paddr_t pa, size_t len) 650 { 651 paddr_t end_pa = 0; 652 653 if (ADD_OVERFLOW(pa, len - 1, &end_pa)) 654 return false; 655 return core_mmu_check_max_pa(end_pa); 656 } 657 658 #ifdef CFG_CORE_PHYS_RELOCATABLE 659 /* 660 * core_mmu_set_secure_memory() - set physical secure memory range 661 * @base: base address of secure memory 662 * @size: size of secure memory 663 * 664 * The physical secure memory range is not known in advance when OP-TEE is 665 * relocatable, this information must be supplied once during boot before 666 * the translation tables can be initialized and the MMU enabled. 667 */ 668 void core_mmu_set_secure_memory(paddr_t base, size_t size); 669 #endif 670 671 /* 672 * core_mmu_get_secure_memory() - get physical secure memory range 673 * @base: base address of secure memory 674 * @size: size of secure memory 675 * 676 * The physical secure memory range returned covers at least the memory 677 * range used by OP-TEE Core, but may cover more memory depending on the 678 * configuration. 679 */ 680 void core_mmu_get_secure_memory(paddr_t *base, paddr_size_t *size); 681 682 /* 683 * core_mmu_get_ta_range() - get physical memory range reserved for TAs 684 * @base: [out] range base address ref or NULL 685 * @size: [out] range size ref or NULL 686 */ 687 void core_mmu_get_ta_range(paddr_t *base, size_t *size); 688 689 #endif /*__ASSEMBLER__*/ 690 691 #endif /* CORE_MMU_H */ 692