1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 #ifndef __MM_CORE_MMU_H 7 #define __MM_CORE_MMU_H 8 9 #ifndef __ASSEMBLER__ 10 #include <assert.h> 11 #include <compiler.h> 12 #include <kernel/user_ta.h> 13 #include <mm/tee_mmu_types.h> 14 #include <types_ext.h> 15 #include <util.h> 16 #endif 17 18 #include <mm/core_mmu_arch.h> 19 #include <platform_config.h> 20 21 /* A small page is the smallest unit of memory that can be mapped */ 22 #define SMALL_PAGE_SIZE BIT(SMALL_PAGE_SHIFT) 23 #define SMALL_PAGE_MASK ((paddr_t)SMALL_PAGE_SIZE - 1) 24 25 /* 26 * PGDIR is the translation table above the translation table that holds 27 * the pages. 28 */ 29 #define CORE_MMU_PGDIR_SIZE BIT(CORE_MMU_PGDIR_SHIFT) 30 #define CORE_MMU_PGDIR_MASK ((paddr_t)CORE_MMU_PGDIR_SIZE - 1) 31 32 /* TA user space code, data, stack and heap are mapped using this granularity */ 33 #define CORE_MMU_USER_CODE_SIZE BIT(CORE_MMU_USER_CODE_SHIFT) 34 #define CORE_MMU_USER_CODE_MASK ((paddr_t)CORE_MMU_USER_CODE_SIZE - 1) 35 36 /* TA user space parameters are mapped using this granularity */ 37 #define CORE_MMU_USER_PARAM_SIZE BIT(CORE_MMU_USER_PARAM_SHIFT) 38 #define CORE_MMU_USER_PARAM_MASK ((paddr_t)CORE_MMU_USER_PARAM_SIZE - 1) 39 40 /* 41 * Identify mapping constraint: virtual base address is the physical start addr. 42 * If platform did not set some macros, some get default value. 43 */ 44 #ifndef TEE_RAM_VA_SIZE 45 #define TEE_RAM_VA_SIZE CORE_MMU_PGDIR_SIZE 46 #endif 47 48 #ifndef TEE_LOAD_ADDR 49 #define TEE_LOAD_ADDR TEE_RAM_START 50 #endif 51 52 #ifndef STACK_ALIGNMENT 53 #define STACK_ALIGNMENT (sizeof(long) * U(2)) 54 #endif 55 56 #ifndef __ASSEMBLER__ 57 /* 58 * Memory area type: 59 * MEM_AREA_END: Reserved, marks the end of a table of mapping areas. 60 * MEM_AREA_TEE_RAM: core RAM (read/write/executable, secure, reserved to TEE) 61 * MEM_AREA_TEE_RAM_RX: core private read-only/executable memory (secure) 62 * MEM_AREA_TEE_RAM_RO: core private read-only/non-executable memory (secure) 63 * MEM_AREA_TEE_RAM_RW: core private read/write/non-executable memory (secure) 64 * MEM_AREA_INIT_RAM_RO: init private read-only/non-executable memory (secure) 65 * MEM_AREA_INIT_RAM_RX: init private read-only/executable memory (secure) 66 * MEM_AREA_NEX_RAM_RO: nexus private read-only/non-executable memory (secure) 67 * MEM_AREA_NEX_RAM_RW: nexus private r/w/non-executable memory (secure) 68 * MEM_AREA_TEE_COHERENT: teecore coherent RAM (secure, reserved to TEE) 69 * MEM_AREA_TEE_ASAN: core address sanitizer RAM (secure, reserved to TEE) 70 * MEM_AREA_IDENTITY_MAP_RX: core identity mapped r/o executable memory (secure) 71 * MEM_AREA_TA_RAM: Secure RAM where teecore loads/exec TA instances. 72 * MEM_AREA_NSEC_SHM: NonSecure shared RAM between NSec and TEE. 73 * MEM_AREA_NEX_NSEC_SHM: nexus non-secure shared RAM between NSec and TEE. 74 * MEM_AREA_RAM_NSEC: NonSecure RAM storing data 75 * MEM_AREA_RAM_SEC: Secure RAM storing some secrets 76 * MEM_AREA_ROM_SEC: Secure read only memory storing some secrets 77 * MEM_AREA_IO_NSEC: NonSecure HW mapped registers 78 * MEM_AREA_IO_SEC: Secure HW mapped registers 79 * MEM_AREA_EXT_DT: Memory loads external device tree 80 * MEM_AREA_MANIFEST_DT: Memory loads manifest device tree 81 * MEM_AREA_TRANSFER_LIST: Memory area mapped for Transfer List 82 * MEM_AREA_RES_VASPACE: Reserved virtual memory space 83 * MEM_AREA_SHM_VASPACE: Virtual memory space for dynamic shared memory buffers 84 * MEM_AREA_TS_VASPACE: TS va space, only used with phys_to_virt() 85 * MEM_AREA_DDR_OVERALL: Overall DDR address range, candidate to dynamic shm. 86 * MEM_AREA_SEC_RAM_OVERALL: Whole secure RAM 87 * MEM_AREA_MAXTYPE: lower invalid 'type' value 88 */ 89 enum teecore_memtypes { 90 MEM_AREA_END = 0, 91 MEM_AREA_TEE_RAM, 92 MEM_AREA_TEE_RAM_RX, 93 MEM_AREA_TEE_RAM_RO, 94 MEM_AREA_TEE_RAM_RW, 95 MEM_AREA_INIT_RAM_RO, 96 MEM_AREA_INIT_RAM_RX, 97 MEM_AREA_NEX_RAM_RO, 98 MEM_AREA_NEX_RAM_RW, 99 MEM_AREA_TEE_COHERENT, 100 MEM_AREA_TEE_ASAN, 101 MEM_AREA_IDENTITY_MAP_RX, 102 MEM_AREA_TA_RAM, 103 MEM_AREA_NSEC_SHM, 104 MEM_AREA_NEX_NSEC_SHM, 105 MEM_AREA_RAM_NSEC, 106 MEM_AREA_RAM_SEC, 107 MEM_AREA_ROM_SEC, 108 MEM_AREA_IO_NSEC, 109 MEM_AREA_IO_SEC, 110 MEM_AREA_EXT_DT, 111 MEM_AREA_MANIFEST_DT, 112 MEM_AREA_TRANSFER_LIST, 113 MEM_AREA_RES_VASPACE, 114 MEM_AREA_SHM_VASPACE, 115 MEM_AREA_TS_VASPACE, 116 MEM_AREA_PAGER_VASPACE, 117 MEM_AREA_SDP_MEM, 118 MEM_AREA_DDR_OVERALL, 119 MEM_AREA_SEC_RAM_OVERALL, 120 MEM_AREA_MAXTYPE 121 }; 122 123 static inline const char *teecore_memtype_name(enum teecore_memtypes type) 124 { 125 static const char * const names[] = { 126 [MEM_AREA_END] = "END", 127 [MEM_AREA_TEE_RAM] = "TEE_RAM_RWX", 128 [MEM_AREA_TEE_RAM_RX] = "TEE_RAM_RX", 129 [MEM_AREA_TEE_RAM_RO] = "TEE_RAM_RO", 130 [MEM_AREA_TEE_RAM_RW] = "TEE_RAM_RW", 131 [MEM_AREA_INIT_RAM_RO] = "INIT_RAM_RO", 132 [MEM_AREA_INIT_RAM_RX] = "INIT_RAM_RX", 133 [MEM_AREA_NEX_RAM_RO] = "NEX_RAM_RO", 134 [MEM_AREA_NEX_RAM_RW] = "NEX_RAM_RW", 135 [MEM_AREA_TEE_ASAN] = "TEE_ASAN", 136 [MEM_AREA_IDENTITY_MAP_RX] = "IDENTITY_MAP_RX", 137 [MEM_AREA_TEE_COHERENT] = "TEE_COHERENT", 138 [MEM_AREA_TA_RAM] = "TA_RAM", 139 [MEM_AREA_NSEC_SHM] = "NSEC_SHM", 140 [MEM_AREA_NEX_NSEC_SHM] = "NEX_NSEC_SHM", 141 [MEM_AREA_RAM_NSEC] = "RAM_NSEC", 142 [MEM_AREA_RAM_SEC] = "RAM_SEC", 143 [MEM_AREA_ROM_SEC] = "ROM_SEC", 144 [MEM_AREA_IO_NSEC] = "IO_NSEC", 145 [MEM_AREA_IO_SEC] = "IO_SEC", 146 [MEM_AREA_EXT_DT] = "EXT_DT", 147 [MEM_AREA_MANIFEST_DT] = "MANIFEST_DT", 148 [MEM_AREA_TRANSFER_LIST] = "TRANSFER_LIST", 149 [MEM_AREA_RES_VASPACE] = "RES_VASPACE", 150 [MEM_AREA_SHM_VASPACE] = "SHM_VASPACE", 151 [MEM_AREA_TS_VASPACE] = "TS_VASPACE", 152 [MEM_AREA_PAGER_VASPACE] = "PAGER_VASPACE", 153 [MEM_AREA_SDP_MEM] = "SDP_MEM", 154 [MEM_AREA_DDR_OVERALL] = "DDR_OVERALL", 155 [MEM_AREA_SEC_RAM_OVERALL] = "SEC_RAM_OVERALL", 156 }; 157 158 COMPILE_TIME_ASSERT(ARRAY_SIZE(names) == MEM_AREA_MAXTYPE); 159 return names[type]; 160 } 161 162 #ifdef CFG_CORE_RWDATA_NOEXEC 163 #define MEM_AREA_TEE_RAM_RW_DATA MEM_AREA_TEE_RAM_RW 164 #else 165 #define MEM_AREA_TEE_RAM_RW_DATA MEM_AREA_TEE_RAM 166 #endif 167 168 struct core_mmu_phys_mem { 169 const char *name; 170 enum teecore_memtypes type; 171 __extension__ union { 172 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 173 struct { 174 uint32_t lo_addr; 175 uint32_t hi_addr; 176 }; 177 #endif 178 paddr_t addr; 179 }; 180 __extension__ union { 181 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 182 struct { 183 uint32_t lo_size; 184 uint32_t hi_size; 185 }; 186 #endif 187 paddr_size_t size; 188 }; 189 }; 190 191 #define __register_memory(_name, _type, _addr, _size, _section) \ 192 SCATTERED_ARRAY_DEFINE_ITEM(_section, struct core_mmu_phys_mem) = \ 193 { .name = (_name), .type = (_type), .addr = (_addr), \ 194 .size = (_size) } 195 196 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 197 #define __register_memory_ul(_name, _type, _addr, _size, _section) \ 198 SCATTERED_ARRAY_DEFINE_ITEM(_section, struct core_mmu_phys_mem) = \ 199 { .name = (_name), .type = (_type), .lo_addr = (_addr), \ 200 .lo_size = (_size) } 201 #else 202 #define __register_memory_ul(_name, _type, _addr, _size, _section) \ 203 __register_memory(_name, _type, _addr, _size, _section) 204 #endif 205 206 #define register_phys_mem(type, addr, size) \ 207 __register_memory(#addr, (type), (addr), (size), \ 208 phys_mem_map) 209 210 #define register_phys_mem_ul(type, addr, size) \ 211 __register_memory_ul(#addr, (type), (addr), (size), \ 212 phys_mem_map) 213 214 /* Same as register_phys_mem() but with PGDIR_SIZE granularity */ 215 #define register_phys_mem_pgdir(type, addr, size) \ 216 __register_memory(#addr, type, ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \ 217 ROUNDUP(size + addr - \ 218 ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \ 219 CORE_MMU_PGDIR_SIZE), phys_mem_map) 220 221 #ifdef CFG_SECURE_DATA_PATH 222 #define register_sdp_mem(addr, size) \ 223 __register_memory(#addr, MEM_AREA_SDP_MEM, (addr), (size), \ 224 phys_sdp_mem) 225 #else 226 #define register_sdp_mem(addr, size) \ 227 static int CONCAT(__register_sdp_mem_unused, __COUNTER__) \ 228 __unused 229 #endif 230 231 /* register_dynamic_shm() is deprecated, please use register_ddr() instead */ 232 #define register_dynamic_shm(addr, size) \ 233 __register_memory(#addr, MEM_AREA_DDR_OVERALL, (addr), (size), \ 234 phys_ddr_overall_compat) 235 236 /* 237 * register_ddr() - Define a memory range 238 * @addr: Base address 239 * @size: Length 240 * 241 * This macro can be used multiple times to define disjoint ranges. While 242 * initializing holes are carved out of these ranges where it overlaps with 243 * special memory, for instance memory registered with register_sdp_mem(). 244 * 245 * The memory that remains is accepted as non-secure shared memory when 246 * communicating with normal world. 247 * 248 * This macro is an alternative to supply the memory description with a 249 * devicetree blob. 250 */ 251 #define register_ddr(addr, size) \ 252 __register_memory(#addr, MEM_AREA_DDR_OVERALL, (addr), \ 253 (size), phys_ddr_overall) 254 255 #define phys_ddr_overall_begin \ 256 SCATTERED_ARRAY_BEGIN(phys_ddr_overall, struct core_mmu_phys_mem) 257 258 #define phys_ddr_overall_end \ 259 SCATTERED_ARRAY_END(phys_ddr_overall, struct core_mmu_phys_mem) 260 261 #define phys_ddr_overall_compat_begin \ 262 SCATTERED_ARRAY_BEGIN(phys_ddr_overall_compat, struct core_mmu_phys_mem) 263 264 #define phys_ddr_overall_compat_end \ 265 SCATTERED_ARRAY_END(phys_ddr_overall_compat, struct core_mmu_phys_mem) 266 267 #define phys_sdp_mem_begin \ 268 SCATTERED_ARRAY_BEGIN(phys_sdp_mem, struct core_mmu_phys_mem) 269 270 #define phys_sdp_mem_end \ 271 SCATTERED_ARRAY_END(phys_sdp_mem, struct core_mmu_phys_mem) 272 273 #define phys_mem_map_begin \ 274 SCATTERED_ARRAY_BEGIN(phys_mem_map, struct core_mmu_phys_mem) 275 276 #define phys_mem_map_end \ 277 SCATTERED_ARRAY_END(phys_mem_map, struct core_mmu_phys_mem) 278 279 #ifdef CFG_CORE_RESERVED_SHM 280 /* Default NSec shared memory allocated from NSec world */ 281 extern unsigned long default_nsec_shm_paddr; 282 extern unsigned long default_nsec_shm_size; 283 #endif 284 285 /* 286 * Physical load address of OP-TEE updated during boot if needed to reflect 287 * the value used. 288 */ 289 #ifdef CFG_CORE_PHYS_RELOCATABLE 290 extern unsigned long core_mmu_tee_load_pa; 291 #else 292 extern const unsigned long core_mmu_tee_load_pa; 293 #endif 294 295 void core_init_mmu_map(unsigned long seed, struct core_mmu_config *cfg); 296 void core_init_mmu_regs(struct core_mmu_config *cfg); 297 298 /* Arch specific function to help optimizing 1 MMU xlat table */ 299 bool core_mmu_prefer_tee_ram_at_top(paddr_t paddr); 300 301 /* 302 * struct mmu_partition - stores MMU partition. 303 * 304 * Basically it represent whole MMU mapping. It is possible 305 * to create multiple partitions, and change them in runtime, 306 * effectively changing how OP-TEE sees memory. 307 * This is opaque struct which is defined differently for 308 * v7 and LPAE MMUs 309 * 310 * This structure used mostly when virtualization is enabled. 311 * When CFG_NS_VIRTUALIZATION==n only default partition exists. 312 */ 313 struct mmu_partition; 314 315 /* 316 * core_mmu_get_user_va_range() - Return range of user va space 317 * @base: Lowest user virtual address 318 * @size: Size in bytes of user address space 319 */ 320 void core_mmu_get_user_va_range(vaddr_t *base, size_t *size); 321 322 /* 323 * enum core_mmu_fault - different kinds of faults 324 * @CORE_MMU_FAULT_ALIGNMENT: alignment fault 325 * @CORE_MMU_FAULT_DEBUG_EVENT: debug event 326 * @CORE_MMU_FAULT_TRANSLATION: translation fault 327 * @CORE_MMU_FAULT_WRITE_PERMISSION: Permission fault during write 328 * @CORE_MMU_FAULT_READ_PERMISSION: Permission fault during read 329 * @CORE_MMU_FAULT_ASYNC_EXTERNAL: asynchronous external abort 330 * @CORE_MMU_FAULT_ACCESS_BIT: access bit fault 331 * @CORE_MMU_FAULT_TAG_CHECK: tag check fault 332 * @CORE_MMU_FAULT_OTHER: Other/unknown fault 333 */ 334 enum core_mmu_fault { 335 CORE_MMU_FAULT_ALIGNMENT, 336 CORE_MMU_FAULT_DEBUG_EVENT, 337 CORE_MMU_FAULT_TRANSLATION, 338 CORE_MMU_FAULT_WRITE_PERMISSION, 339 CORE_MMU_FAULT_READ_PERMISSION, 340 CORE_MMU_FAULT_ASYNC_EXTERNAL, 341 CORE_MMU_FAULT_ACCESS_BIT, 342 CORE_MMU_FAULT_TAG_CHECK, 343 CORE_MMU_FAULT_OTHER, 344 }; 345 346 /* 347 * core_mmu_get_fault_type() - get fault type 348 * @fault_descr: Content of fault status or exception syndrome register 349 * @returns an enum describing the content of fault status register. 350 */ 351 enum core_mmu_fault core_mmu_get_fault_type(uint32_t fault_descr); 352 353 /* 354 * core_mm_type_to_attr() - convert memory type to attribute 355 * @t: memory type 356 * @returns an attribute that can be passed to core_mm_set_entry() and friends 357 */ 358 uint32_t core_mmu_type_to_attr(enum teecore_memtypes t); 359 360 /* 361 * core_mmu_create_user_map() - Create user mode mapping 362 * @uctx: Pointer to user mode context 363 * @map: MMU configuration to use when activating this VA space 364 */ 365 void core_mmu_create_user_map(struct user_mode_ctx *uctx, 366 struct core_mmu_user_map *map); 367 /* 368 * core_mmu_get_user_map() - Reads current MMU configuration for user VA space 369 * @map: MMU configuration for current user VA space. 370 */ 371 void core_mmu_get_user_map(struct core_mmu_user_map *map); 372 373 /* 374 * core_mmu_set_user_map() - Set new MMU configuration for user VA space 375 * @map: User context MMU configuration or NULL to set core VA space 376 * 377 * Activate user VA space mapping and set its ASID if @map is not NULL, 378 * otherwise activate core mapping and set ASID to 0. 379 */ 380 void core_mmu_set_user_map(struct core_mmu_user_map *map); 381 382 /* 383 * struct core_mmu_table_info - Properties for a translation table 384 * @table: Pointer to translation table 385 * @va_base: VA base address of the transaltion table 386 * @level: Translation table level 387 * @next_level: Finer grained translation table level according to @level. 388 * @shift: The shift of each entry in the table 389 * @num_entries: Number of entries in this table. 390 */ 391 struct core_mmu_table_info { 392 void *table; 393 vaddr_t va_base; 394 unsigned num_entries; 395 #ifdef CFG_NS_VIRTUALIZATION 396 struct mmu_partition *prtn; 397 #endif 398 uint8_t level; 399 uint8_t shift; 400 uint8_t next_level; 401 }; 402 403 /* 404 * core_mmu_find_table() - Locates a translation table 405 * @prtn: MMU partition where search should be performed 406 * @va: Virtual address for the table to cover 407 * @max_level: Don't traverse beyond this level 408 * @tbl_info: Pointer to where to store properties. 409 * @return true if a translation table was found, false on error 410 */ 411 bool core_mmu_find_table(struct mmu_partition *prtn, vaddr_t va, 412 unsigned max_level, 413 struct core_mmu_table_info *tbl_info); 414 415 /* 416 * core_mmu_entry_to_finer_grained() - divide mapping at current level into 417 * smaller ones so memory can be mapped with finer granularity 418 * @tbl_info: table where target record located 419 * @idx: index of record for which a pdgir must be setup. 420 * @secure: true/false if pgdir maps secure/non-secure memory (32bit mmu) 421 * @return true on successful, false on error 422 */ 423 bool core_mmu_entry_to_finer_grained(struct core_mmu_table_info *tbl_info, 424 unsigned int idx, bool secure); 425 426 void core_mmu_set_entry_primitive(void *table, size_t level, size_t idx, 427 paddr_t pa, uint32_t attr); 428 429 void core_mmu_get_user_pgdir(struct core_mmu_table_info *pgd_info); 430 431 /* 432 * core_mmu_set_entry() - Set entry in translation table 433 * @tbl_info: Translation table properties 434 * @idx: Index of entry to update 435 * @pa: Physical address to assign entry 436 * @attr: Attributes to assign entry 437 */ 438 void core_mmu_set_entry(struct core_mmu_table_info *tbl_info, unsigned idx, 439 paddr_t pa, uint32_t attr); 440 441 void core_mmu_get_entry_primitive(const void *table, size_t level, size_t idx, 442 paddr_t *pa, uint32_t *attr); 443 444 /* 445 * core_mmu_get_entry() - Get entry from translation table 446 * @tbl_info: Translation table properties 447 * @idx: Index of entry to read 448 * @pa: Physical address is returned here if pa is not NULL 449 * @attr: Attributues are returned here if attr is not NULL 450 */ 451 void core_mmu_get_entry(struct core_mmu_table_info *tbl_info, unsigned idx, 452 paddr_t *pa, uint32_t *attr); 453 454 /* 455 * core_mmu_va2idx() - Translate from virtual address to table index 456 * @tbl_info: Translation table properties 457 * @va: Virtual address to translate 458 * @returns index in transaltion table 459 */ 460 static inline unsigned core_mmu_va2idx(struct core_mmu_table_info *tbl_info, 461 vaddr_t va) 462 { 463 return (va - tbl_info->va_base) >> tbl_info->shift; 464 } 465 466 /* 467 * core_mmu_idx2va() - Translate from table index to virtual address 468 * @tbl_info: Translation table properties 469 * @idx: Index to translate 470 * @returns Virtual address 471 */ 472 static inline vaddr_t core_mmu_idx2va(struct core_mmu_table_info *tbl_info, 473 unsigned idx) 474 { 475 return (idx << tbl_info->shift) + tbl_info->va_base; 476 } 477 478 /* 479 * core_mmu_get_block_offset() - Get offset inside a block/page 480 * @tbl_info: Translation table properties 481 * @pa: Physical address 482 * @returns offset within one block of the translation table 483 */ 484 static inline size_t core_mmu_get_block_offset( 485 struct core_mmu_table_info *tbl_info, paddr_t pa) 486 { 487 return pa & ((1 << tbl_info->shift) - 1); 488 } 489 490 /* 491 * core_mmu_is_dynamic_vaspace() - Check if memory region belongs to 492 * empty virtual address space that is used for dymanic mappings 493 * @mm: memory region to be checked 494 * @returns result of the check 495 */ 496 static inline bool core_mmu_is_dynamic_vaspace(struct tee_mmap_region *mm) 497 { 498 return mm->type == MEM_AREA_RES_VASPACE || 499 mm->type == MEM_AREA_SHM_VASPACE; 500 } 501 502 /* 503 * core_mmu_map_pages() - map list of pages at given virtual address 504 * @vstart: Virtual address where mapping begins 505 * @pages: Array of page addresses 506 * @num_pages: Number of pages 507 * @memtype: Type of memmory to be mapped 508 * 509 * Note: This function asserts that pages are not mapped executeable for 510 * kernel (privileged) mode. 511 * 512 * @returns: TEE_SUCCESS on success, TEE_ERROR_XXX on error 513 */ 514 TEE_Result core_mmu_map_pages(vaddr_t vstart, paddr_t *pages, size_t num_pages, 515 enum teecore_memtypes memtype); 516 517 /* 518 * core_mmu_map_contiguous_pages() - map range of pages at given virtual address 519 * @vstart: Virtual address where mapping begins 520 * @pstart: Physical address of the first page 521 * @num_pages: Number of pages 522 * @memtype: Type of memmory to be mapped 523 * 524 * Note: This function asserts that pages are not mapped executeable for 525 * kernel (privileged) mode. 526 * 527 * @returns: TEE_SUCCESS on success, TEE_ERROR_XXX on error 528 */ 529 TEE_Result core_mmu_map_contiguous_pages(vaddr_t vstart, paddr_t pstart, 530 size_t num_pages, 531 enum teecore_memtypes memtype); 532 533 /* 534 * core_mmu_unmap_pages() - remove mapping at given virtual address 535 * @vstart: Virtual address where mapping begins 536 * @num_pages: Number of pages to unmap 537 */ 538 void core_mmu_unmap_pages(vaddr_t vstart, size_t num_pages); 539 540 /* 541 * core_mmu_user_mapping_is_active() - Report if user mapping is active 542 * @returns true if a user VA space is active, false if user VA space is 543 * inactive. 544 */ 545 bool core_mmu_user_mapping_is_active(void); 546 547 /* 548 * core_mmu_mattr_is_ok() - Check that supplied mem attributes can be used 549 * @returns true if the attributes can be used, false if not. 550 */ 551 bool core_mmu_mattr_is_ok(uint32_t mattr); 552 553 void core_mmu_get_mem_by_type(enum teecore_memtypes type, vaddr_t *s, 554 vaddr_t *e); 555 556 enum teecore_memtypes core_mmu_get_type_by_pa(paddr_t pa); 557 558 /* routines to retreive shared mem configuration */ 559 static inline bool core_mmu_is_shm_cached(void) 560 { 561 return mattr_is_cached(core_mmu_type_to_attr(MEM_AREA_NSEC_SHM)); 562 } 563 564 TEE_Result core_mmu_remove_mapping(enum teecore_memtypes type, void *addr, 565 size_t len); 566 void *core_mmu_add_mapping(enum teecore_memtypes type, paddr_t addr, 567 size_t len); 568 569 /* 570 * core_mmu_find_mapping_exclusive() - Find mapping of specified type and 571 * length. If more than one mapping of 572 * specified type is present, NULL will be 573 * returned. 574 * @type: memory type 575 * @len: length in bytes 576 */ 577 struct tee_mmap_region * 578 core_mmu_find_mapping_exclusive(enum teecore_memtypes type, size_t len); 579 580 /* 581 * tlbi_va_range() - Invalidate TLB for virtual address range 582 * @va: start virtual address, must be a multiple of @granule 583 * @len: length in bytes of range, must be a multiple of @granule 584 * @granule: granularity of mapping, supported values are 585 * CORE_MMU_PGDIR_SIZE or SMALL_PAGE_SIZE. This value must 586 * match the actual mappings. 587 */ 588 void tlbi_va_range(vaddr_t va, size_t len, size_t granule); 589 590 /* 591 * tlbi_va_range_asid() - Invalidate TLB for virtual address range for 592 * a specific ASID 593 * @va: start virtual address, must be a multiple of @granule 594 * @len: length in bytes of range, must be a multiple of @granule 595 * @granule: granularity of mapping, supported values are 596 * CORE_MMU_PGDIR_SIZE or SMALL_PAGE_SIZE. This value must 597 * match the actual mappings. 598 * @asid: Address space identifier 599 */ 600 void tlbi_va_range_asid(vaddr_t va, size_t len, size_t granule, uint32_t asid); 601 602 /* Check cpu mmu enabled or not */ 603 bool cpu_mmu_enabled(void); 604 605 #ifdef CFG_CORE_DYN_SHM 606 /* 607 * Check if platform defines nsec DDR range(s). 608 * Static SHM (MEM_AREA_NSEC_SHM) is not covered by this API as it is 609 * always present. 610 */ 611 bool core_mmu_nsec_ddr_is_defined(void); 612 613 void core_mmu_set_discovered_nsec_ddr(struct core_mmu_phys_mem *start, 614 size_t nelems); 615 #endif 616 617 /* Initialize MMU partition */ 618 void core_init_mmu_prtn(struct mmu_partition *prtn, struct tee_mmap_region *mm); 619 620 unsigned int asid_alloc(void); 621 void asid_free(unsigned int asid); 622 623 #ifdef CFG_SECURE_DATA_PATH 624 /* Alloc and fill SDP memory objects table - table is NULL terminated */ 625 struct mobj **core_sdp_mem_create_mobjs(void); 626 #endif 627 628 #ifdef CFG_NS_VIRTUALIZATION 629 size_t core_mmu_get_total_pages_size(void); 630 struct mmu_partition *core_alloc_mmu_prtn(void *tables); 631 void core_free_mmu_prtn(struct mmu_partition *prtn); 632 void core_mmu_set_prtn(struct mmu_partition *prtn); 633 void core_mmu_set_default_prtn(void); 634 void core_mmu_set_default_prtn_tbl(void); 635 #endif 636 637 void core_mmu_init_virtualization(void); 638 639 /* init some allocation pools */ 640 void core_mmu_init_ta_ram(void); 641 642 void core_init_mmu(struct tee_mmap_region *mm); 643 644 void core_mmu_set_info_table(struct core_mmu_table_info *tbl_info, 645 unsigned int level, vaddr_t va_base, void *table); 646 void core_mmu_populate_user_map(struct core_mmu_table_info *dir_info, 647 struct user_mode_ctx *uctx); 648 void core_mmu_map_region(struct mmu_partition *prtn, 649 struct tee_mmap_region *mm); 650 651 bool arch_va2pa_helper(void *va, paddr_t *pa); 652 653 static inline bool core_mmap_is_end_of_table(const struct tee_mmap_region *mm) 654 { 655 return mm->type == MEM_AREA_END; 656 } 657 658 static inline bool core_mmu_check_end_pa(paddr_t pa, size_t len) 659 { 660 paddr_t end_pa = 0; 661 662 if (ADD_OVERFLOW(pa, len - 1, &end_pa)) 663 return false; 664 return core_mmu_check_max_pa(end_pa); 665 } 666 667 /* 668 * core_mmu_set_secure_memory() - set physical secure memory range 669 * @base: base address of secure memory 670 * @size: size of secure memory 671 * 672 * The physical secure memory range is not known in advance when OP-TEE is 673 * relocatable, this information must be supplied once during boot before 674 * the translation tables can be initialized and the MMU enabled. 675 */ 676 void core_mmu_set_secure_memory(paddr_t base, size_t size); 677 678 /* 679 * core_mmu_get_secure_memory() - get physical secure memory range 680 * @base: base address of secure memory 681 * @size: size of secure memory 682 * 683 * The physical secure memory range returned covers at least the memory 684 * range used by OP-TEE Core, but may cover more memory depending on the 685 * configuration. 686 */ 687 void core_mmu_get_secure_memory(paddr_t *base, paddr_size_t *size); 688 689 /* 690 * core_mmu_get_ta_range() - get physical memory range reserved for TAs 691 * @base: [out] range base address ref or NULL 692 * @size: [out] range size ref or NULL 693 */ 694 void core_mmu_get_ta_range(paddr_t *base, size_t *size); 695 696 #endif /*__ASSEMBLER__*/ 697 698 #endif /* __MM_CORE_MMU_H */ 699