1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 #ifndef CORE_MMU_H 7 #define CORE_MMU_H 8 9 #ifndef __ASSEMBLER__ 10 #include <assert.h> 11 #include <compiler.h> 12 #include <kernel/user_ta.h> 13 #include <mm/tee_mmu_types.h> 14 #include <types_ext.h> 15 #include <util.h> 16 #endif 17 18 #include <mm/core_mmu_arch.h> 19 #include <platform_config.h> 20 21 /* A small page is the smallest unit of memory that can be mapped */ 22 #define SMALL_PAGE_SIZE BIT(SMALL_PAGE_SHIFT) 23 #define SMALL_PAGE_MASK ((paddr_t)SMALL_PAGE_SIZE - 1) 24 25 /* 26 * PGDIR is the translation table above the translation table that holds 27 * the pages. 28 */ 29 #define CORE_MMU_PGDIR_SIZE BIT(CORE_MMU_PGDIR_SHIFT) 30 #define CORE_MMU_PGDIR_MASK ((paddr_t)CORE_MMU_PGDIR_SIZE - 1) 31 32 /* TA user space code, data, stack and heap are mapped using this granularity */ 33 #define CORE_MMU_USER_CODE_SIZE BIT(CORE_MMU_USER_CODE_SHIFT) 34 #define CORE_MMU_USER_CODE_MASK ((paddr_t)CORE_MMU_USER_CODE_SIZE - 1) 35 36 /* TA user space parameters are mapped using this granularity */ 37 #define CORE_MMU_USER_PARAM_SIZE BIT(CORE_MMU_USER_PARAM_SHIFT) 38 #define CORE_MMU_USER_PARAM_MASK ((paddr_t)CORE_MMU_USER_PARAM_SIZE - 1) 39 40 /* 41 * Identify mapping constraint: virtual base address is the physical start addr. 42 * If platform did not set some macros, some get default value. 43 */ 44 #ifndef TEE_RAM_VA_SIZE 45 #define TEE_RAM_VA_SIZE CORE_MMU_PGDIR_SIZE 46 #endif 47 48 #ifndef TEE_LOAD_ADDR 49 #define TEE_LOAD_ADDR TEE_RAM_START 50 #endif 51 52 #ifndef STACK_ALIGNMENT 53 #define STACK_ALIGNMENT (sizeof(long) * U(2)) 54 #endif 55 56 #ifndef __ASSEMBLER__ 57 /* 58 * Memory area type: 59 * MEM_AREA_END: Reserved, marks the end of a table of mapping areas. 60 * MEM_AREA_TEE_RAM: core RAM (read/write/executable, secure, reserved to TEE) 61 * MEM_AREA_TEE_RAM_RX: core private read-only/executable memory (secure) 62 * MEM_AREA_TEE_RAM_RO: core private read-only/non-executable memory (secure) 63 * MEM_AREA_TEE_RAM_RW: core private read/write/non-executable memory (secure) 64 * MEM_AREA_INIT_RAM_RO: init private read-only/non-executable memory (secure) 65 * MEM_AREA_INIT_RAM_RX: init private read-only/executable memory (secure) 66 * MEM_AREA_NEX_RAM_RO: nexus private read-only/non-executable memory (secure) 67 * MEM_AREA_NEX_RAM_RW: nexus private r/w/non-executable memory (secure) 68 * MEM_AREA_TEE_COHERENT: teecore coherent RAM (secure, reserved to TEE) 69 * MEM_AREA_TEE_ASAN: core address sanitizer RAM (secure, reserved to TEE) 70 * MEM_AREA_IDENTITY_MAP_RX: core identity mapped r/o executable memory (secure) 71 * MEM_AREA_TA_RAM: Secure RAM where teecore loads/exec TA instances. 72 * MEM_AREA_NSEC_SHM: NonSecure shared RAM between NSec and TEE. 73 * MEM_AREA_NEX_NSEC_SHM: nexus non-secure shared RAM between NSec and TEE. 74 * MEM_AREA_RAM_NSEC: NonSecure RAM storing data 75 * MEM_AREA_RAM_SEC: Secure RAM storing some secrets 76 * MEM_AREA_IO_NSEC: NonSecure HW mapped registers 77 * MEM_AREA_IO_SEC: Secure HW mapped registers 78 * MEM_AREA_EXT_DT: Memory loads external device tree 79 * MEM_AREA_MANIFEST_DT: Memory loads manifest device tree 80 * MEM_AREA_RES_VASPACE: Reserved virtual memory space 81 * MEM_AREA_SHM_VASPACE: Virtual memory space for dynamic shared memory buffers 82 * MEM_AREA_TS_VASPACE: TS va space, only used with phys_to_virt() 83 * MEM_AREA_DDR_OVERALL: Overall DDR address range, candidate to dynamic shm. 84 * MEM_AREA_SEC_RAM_OVERALL: Whole secure RAM 85 * MEM_AREA_MAXTYPE: lower invalid 'type' value 86 */ 87 enum teecore_memtypes { 88 MEM_AREA_END = 0, 89 MEM_AREA_TEE_RAM, 90 MEM_AREA_TEE_RAM_RX, 91 MEM_AREA_TEE_RAM_RO, 92 MEM_AREA_TEE_RAM_RW, 93 MEM_AREA_INIT_RAM_RO, 94 MEM_AREA_INIT_RAM_RX, 95 MEM_AREA_NEX_RAM_RO, 96 MEM_AREA_NEX_RAM_RW, 97 MEM_AREA_TEE_COHERENT, 98 MEM_AREA_TEE_ASAN, 99 MEM_AREA_IDENTITY_MAP_RX, 100 MEM_AREA_TA_RAM, 101 MEM_AREA_NSEC_SHM, 102 MEM_AREA_NEX_NSEC_SHM, 103 MEM_AREA_RAM_NSEC, 104 MEM_AREA_RAM_SEC, 105 MEM_AREA_IO_NSEC, 106 MEM_AREA_IO_SEC, 107 MEM_AREA_EXT_DT, 108 MEM_AREA_MANIFEST_DT, 109 MEM_AREA_RES_VASPACE, 110 MEM_AREA_SHM_VASPACE, 111 MEM_AREA_TS_VASPACE, 112 MEM_AREA_PAGER_VASPACE, 113 MEM_AREA_SDP_MEM, 114 MEM_AREA_DDR_OVERALL, 115 MEM_AREA_SEC_RAM_OVERALL, 116 MEM_AREA_MAXTYPE 117 }; 118 119 static inline const char *teecore_memtype_name(enum teecore_memtypes type) 120 { 121 static const char * const names[] = { 122 [MEM_AREA_END] = "END", 123 [MEM_AREA_TEE_RAM] = "TEE_RAM_RWX", 124 [MEM_AREA_TEE_RAM_RX] = "TEE_RAM_RX", 125 [MEM_AREA_TEE_RAM_RO] = "TEE_RAM_RO", 126 [MEM_AREA_TEE_RAM_RW] = "TEE_RAM_RW", 127 [MEM_AREA_INIT_RAM_RO] = "INIT_RAM_RO", 128 [MEM_AREA_INIT_RAM_RX] = "INIT_RAM_RX", 129 [MEM_AREA_NEX_RAM_RO] = "NEX_RAM_RO", 130 [MEM_AREA_NEX_RAM_RW] = "NEX_RAM_RW", 131 [MEM_AREA_TEE_ASAN] = "TEE_ASAN", 132 [MEM_AREA_IDENTITY_MAP_RX] = "IDENTITY_MAP_RX", 133 [MEM_AREA_TEE_COHERENT] = "TEE_COHERENT", 134 [MEM_AREA_TA_RAM] = "TA_RAM", 135 [MEM_AREA_NSEC_SHM] = "NSEC_SHM", 136 [MEM_AREA_NEX_NSEC_SHM] = "NEX_NSEC_SHM", 137 [MEM_AREA_RAM_NSEC] = "RAM_NSEC", 138 [MEM_AREA_RAM_SEC] = "RAM_SEC", 139 [MEM_AREA_IO_NSEC] = "IO_NSEC", 140 [MEM_AREA_IO_SEC] = "IO_SEC", 141 [MEM_AREA_EXT_DT] = "EXT_DT", 142 [MEM_AREA_MANIFEST_DT] = "MANIFEST_DT", 143 [MEM_AREA_RES_VASPACE] = "RES_VASPACE", 144 [MEM_AREA_SHM_VASPACE] = "SHM_VASPACE", 145 [MEM_AREA_TS_VASPACE] = "TS_VASPACE", 146 [MEM_AREA_PAGER_VASPACE] = "PAGER_VASPACE", 147 [MEM_AREA_SDP_MEM] = "SDP_MEM", 148 [MEM_AREA_DDR_OVERALL] = "DDR_OVERALL", 149 [MEM_AREA_SEC_RAM_OVERALL] = "SEC_RAM_OVERALL", 150 }; 151 152 COMPILE_TIME_ASSERT(ARRAY_SIZE(names) == MEM_AREA_MAXTYPE); 153 return names[type]; 154 } 155 156 #ifdef CFG_CORE_RWDATA_NOEXEC 157 #define MEM_AREA_TEE_RAM_RW_DATA MEM_AREA_TEE_RAM_RW 158 #else 159 #define MEM_AREA_TEE_RAM_RW_DATA MEM_AREA_TEE_RAM 160 #endif 161 162 struct core_mmu_phys_mem { 163 const char *name; 164 enum teecore_memtypes type; 165 __extension__ union { 166 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 167 struct { 168 uint32_t lo_addr; 169 uint32_t hi_addr; 170 }; 171 #endif 172 paddr_t addr; 173 }; 174 __extension__ union { 175 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 176 struct { 177 uint32_t lo_size; 178 uint32_t hi_size; 179 }; 180 #endif 181 paddr_size_t size; 182 }; 183 }; 184 185 #define __register_memory(_name, _type, _addr, _size, _section) \ 186 SCATTERED_ARRAY_DEFINE_ITEM(_section, struct core_mmu_phys_mem) = \ 187 { .name = (_name), .type = (_type), .addr = (_addr), \ 188 .size = (_size) } 189 190 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 191 #define __register_memory_ul(_name, _type, _addr, _size, _section) \ 192 SCATTERED_ARRAY_DEFINE_ITEM(_section, struct core_mmu_phys_mem) = \ 193 { .name = (_name), .type = (_type), .lo_addr = (_addr), \ 194 .lo_size = (_size) } 195 #else 196 #define __register_memory_ul(_name, _type, _addr, _size, _section) \ 197 __register_memory(_name, _type, _addr, _size, _section) 198 #endif 199 200 #define register_phys_mem(type, addr, size) \ 201 __register_memory(#addr, (type), (addr), (size), \ 202 phys_mem_map) 203 204 #define register_phys_mem_ul(type, addr, size) \ 205 __register_memory_ul(#addr, (type), (addr), (size), \ 206 phys_mem_map) 207 208 /* Same as register_phys_mem() but with PGDIR_SIZE granularity */ 209 #define register_phys_mem_pgdir(type, addr, size) \ 210 __register_memory(#addr, type, ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \ 211 ROUNDUP(size + addr - \ 212 ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \ 213 CORE_MMU_PGDIR_SIZE), phys_mem_map) 214 215 #ifdef CFG_SECURE_DATA_PATH 216 #define register_sdp_mem(addr, size) \ 217 __register_memory(#addr, MEM_AREA_SDP_MEM, (addr), (size), \ 218 phys_sdp_mem) 219 #else 220 #define register_sdp_mem(addr, size) \ 221 static int CONCAT(__register_sdp_mem_unused, __COUNTER__) \ 222 __unused 223 #endif 224 225 /* register_dynamic_shm() is deprecated, please use register_ddr() instead */ 226 #define register_dynamic_shm(addr, size) \ 227 __register_memory(#addr, MEM_AREA_DDR_OVERALL, (addr), (size), \ 228 phys_ddr_overall_compat) 229 230 /* 231 * register_ddr() - Define a memory range 232 * @addr: Base address 233 * @size: Length 234 * 235 * This macro can be used multiple times to define disjoint ranges. While 236 * initializing holes are carved out of these ranges where it overlaps with 237 * special memory, for instance memory registered with register_sdp_mem(). 238 * 239 * The memory that remains is accepted as non-secure shared memory when 240 * communicating with normal world. 241 * 242 * This macro is an alternative to supply the memory description with a 243 * devicetree blob. 244 */ 245 #define register_ddr(addr, size) \ 246 __register_memory(#addr, MEM_AREA_DDR_OVERALL, (addr), \ 247 (size), phys_ddr_overall) 248 249 #define phys_ddr_overall_begin \ 250 SCATTERED_ARRAY_BEGIN(phys_ddr_overall, struct core_mmu_phys_mem) 251 252 #define phys_ddr_overall_end \ 253 SCATTERED_ARRAY_END(phys_ddr_overall, struct core_mmu_phys_mem) 254 255 #define phys_ddr_overall_compat_begin \ 256 SCATTERED_ARRAY_BEGIN(phys_ddr_overall_compat, struct core_mmu_phys_mem) 257 258 #define phys_ddr_overall_compat_end \ 259 SCATTERED_ARRAY_END(phys_ddr_overall_compat, struct core_mmu_phys_mem) 260 261 #define phys_sdp_mem_begin \ 262 SCATTERED_ARRAY_BEGIN(phys_sdp_mem, struct core_mmu_phys_mem) 263 264 #define phys_sdp_mem_end \ 265 SCATTERED_ARRAY_END(phys_sdp_mem, struct core_mmu_phys_mem) 266 267 #define phys_mem_map_begin \ 268 SCATTERED_ARRAY_BEGIN(phys_mem_map, struct core_mmu_phys_mem) 269 270 #define phys_mem_map_end \ 271 SCATTERED_ARRAY_END(phys_mem_map, struct core_mmu_phys_mem) 272 273 #ifdef CFG_CORE_RESERVED_SHM 274 /* Default NSec shared memory allocated from NSec world */ 275 extern unsigned long default_nsec_shm_paddr; 276 extern unsigned long default_nsec_shm_size; 277 #endif 278 279 /* 280 * Physical load address of OP-TEE updated during boot if needed to reflect 281 * the value used. 282 */ 283 #ifdef CFG_CORE_PHYS_RELOCATABLE 284 extern unsigned long core_mmu_tee_load_pa; 285 #else 286 extern const unsigned long core_mmu_tee_load_pa; 287 #endif 288 289 void core_init_mmu_map(unsigned long seed, struct core_mmu_config *cfg); 290 void core_init_mmu_regs(struct core_mmu_config *cfg); 291 292 /* Arch specific function to help optimizing 1 MMU xlat table */ 293 bool core_mmu_prefer_tee_ram_at_top(paddr_t paddr); 294 295 /* 296 * struct mmu_partition - stores MMU partition. 297 * 298 * Basically it represent whole MMU mapping. It is possible 299 * to create multiple partitions, and change them in runtime, 300 * effectively changing how OP-TEE sees memory. 301 * This is opaque struct which is defined differently for 302 * v7 and LPAE MMUs 303 * 304 * This structure used mostly when virtualization is enabled. 305 * When CFG_NS_VIRTUALIZATION==n only default partition exists. 306 */ 307 struct mmu_partition; 308 309 /* 310 * core_mmu_get_user_va_range() - Return range of user va space 311 * @base: Lowest user virtual address 312 * @size: Size in bytes of user address space 313 */ 314 void core_mmu_get_user_va_range(vaddr_t *base, size_t *size); 315 316 /* 317 * enum core_mmu_fault - different kinds of faults 318 * @CORE_MMU_FAULT_ALIGNMENT: alignment fault 319 * @CORE_MMU_FAULT_DEBUG_EVENT: debug event 320 * @CORE_MMU_FAULT_TRANSLATION: translation fault 321 * @CORE_MMU_FAULT_WRITE_PERMISSION: Permission fault during write 322 * @CORE_MMU_FAULT_READ_PERMISSION: Permission fault during read 323 * @CORE_MMU_FAULT_ASYNC_EXTERNAL: asynchronous external abort 324 * @CORE_MMU_FAULT_ACCESS_BIT: access bit fault 325 * @CORE_MMU_FAULT_TAG_CHECK: tag check fault 326 * @CORE_MMU_FAULT_OTHER: Other/unknown fault 327 */ 328 enum core_mmu_fault { 329 CORE_MMU_FAULT_ALIGNMENT, 330 CORE_MMU_FAULT_DEBUG_EVENT, 331 CORE_MMU_FAULT_TRANSLATION, 332 CORE_MMU_FAULT_WRITE_PERMISSION, 333 CORE_MMU_FAULT_READ_PERMISSION, 334 CORE_MMU_FAULT_ASYNC_EXTERNAL, 335 CORE_MMU_FAULT_ACCESS_BIT, 336 CORE_MMU_FAULT_TAG_CHECK, 337 CORE_MMU_FAULT_OTHER, 338 }; 339 340 /* 341 * core_mmu_get_fault_type() - get fault type 342 * @fault_descr: Content of fault status or exception syndrome register 343 * @returns an enum describing the content of fault status register. 344 */ 345 enum core_mmu_fault core_mmu_get_fault_type(uint32_t fault_descr); 346 347 /* 348 * core_mm_type_to_attr() - convert memory type to attribute 349 * @t: memory type 350 * @returns an attribute that can be passed to core_mm_set_entry() and friends 351 */ 352 uint32_t core_mmu_type_to_attr(enum teecore_memtypes t); 353 354 /* 355 * core_mmu_create_user_map() - Create user mode mapping 356 * @uctx: Pointer to user mode context 357 * @map: MMU configuration to use when activating this VA space 358 */ 359 void core_mmu_create_user_map(struct user_mode_ctx *uctx, 360 struct core_mmu_user_map *map); 361 /* 362 * core_mmu_get_user_map() - Reads current MMU configuration for user VA space 363 * @map: MMU configuration for current user VA space. 364 */ 365 void core_mmu_get_user_map(struct core_mmu_user_map *map); 366 367 /* 368 * core_mmu_set_user_map() - Set new MMU configuration for user VA space 369 * @map: User context MMU configuration or NULL to set core VA space 370 * 371 * Activate user VA space mapping and set its ASID if @map is not NULL, 372 * otherwise activate core mapping and set ASID to 0. 373 */ 374 void core_mmu_set_user_map(struct core_mmu_user_map *map); 375 376 /* 377 * struct core_mmu_table_info - Properties for a translation table 378 * @table: Pointer to translation table 379 * @va_base: VA base address of the transaltion table 380 * @level: Translation table level 381 * @next_level: Finer grained translation table level according to @level. 382 * @shift: The shift of each entry in the table 383 * @num_entries: Number of entries in this table. 384 */ 385 struct core_mmu_table_info { 386 void *table; 387 vaddr_t va_base; 388 unsigned num_entries; 389 #ifdef CFG_NS_VIRTUALIZATION 390 struct mmu_partition *prtn; 391 #endif 392 uint8_t level; 393 uint8_t shift; 394 uint8_t next_level; 395 }; 396 397 /* 398 * core_mmu_find_table() - Locates a translation table 399 * @prtn: MMU partition where search should be performed 400 * @va: Virtual address for the table to cover 401 * @max_level: Don't traverse beyond this level 402 * @tbl_info: Pointer to where to store properties. 403 * @return true if a translation table was found, false on error 404 */ 405 bool core_mmu_find_table(struct mmu_partition *prtn, vaddr_t va, 406 unsigned max_level, 407 struct core_mmu_table_info *tbl_info); 408 409 /* 410 * core_mmu_entry_to_finer_grained() - divide mapping at current level into 411 * smaller ones so memory can be mapped with finer granularity 412 * @tbl_info: table where target record located 413 * @idx: index of record for which a pdgir must be setup. 414 * @secure: true/false if pgdir maps secure/non-secure memory (32bit mmu) 415 * @return true on successful, false on error 416 */ 417 bool core_mmu_entry_to_finer_grained(struct core_mmu_table_info *tbl_info, 418 unsigned int idx, bool secure); 419 420 void core_mmu_set_entry_primitive(void *table, size_t level, size_t idx, 421 paddr_t pa, uint32_t attr); 422 423 void core_mmu_get_user_pgdir(struct core_mmu_table_info *pgd_info); 424 425 /* 426 * core_mmu_set_entry() - Set entry in translation table 427 * @tbl_info: Translation table properties 428 * @idx: Index of entry to update 429 * @pa: Physical address to assign entry 430 * @attr: Attributes to assign entry 431 */ 432 void core_mmu_set_entry(struct core_mmu_table_info *tbl_info, unsigned idx, 433 paddr_t pa, uint32_t attr); 434 435 void core_mmu_get_entry_primitive(const void *table, size_t level, size_t idx, 436 paddr_t *pa, uint32_t *attr); 437 438 /* 439 * core_mmu_get_entry() - Get entry from translation table 440 * @tbl_info: Translation table properties 441 * @idx: Index of entry to read 442 * @pa: Physical address is returned here if pa is not NULL 443 * @attr: Attributues are returned here if attr is not NULL 444 */ 445 void core_mmu_get_entry(struct core_mmu_table_info *tbl_info, unsigned idx, 446 paddr_t *pa, uint32_t *attr); 447 448 /* 449 * core_mmu_va2idx() - Translate from virtual address to table index 450 * @tbl_info: Translation table properties 451 * @va: Virtual address to translate 452 * @returns index in transaltion table 453 */ 454 static inline unsigned core_mmu_va2idx(struct core_mmu_table_info *tbl_info, 455 vaddr_t va) 456 { 457 return (va - tbl_info->va_base) >> tbl_info->shift; 458 } 459 460 /* 461 * core_mmu_idx2va() - Translate from table index to virtual address 462 * @tbl_info: Translation table properties 463 * @idx: Index to translate 464 * @returns Virtual address 465 */ 466 static inline vaddr_t core_mmu_idx2va(struct core_mmu_table_info *tbl_info, 467 unsigned idx) 468 { 469 return (idx << tbl_info->shift) + tbl_info->va_base; 470 } 471 472 /* 473 * core_mmu_get_block_offset() - Get offset inside a block/page 474 * @tbl_info: Translation table properties 475 * @pa: Physical address 476 * @returns offset within one block of the translation table 477 */ 478 static inline size_t core_mmu_get_block_offset( 479 struct core_mmu_table_info *tbl_info, paddr_t pa) 480 { 481 return pa & ((1 << tbl_info->shift) - 1); 482 } 483 484 /* 485 * core_mmu_is_dynamic_vaspace() - Check if memory region belongs to 486 * empty virtual address space that is used for dymanic mappings 487 * @mm: memory region to be checked 488 * @returns result of the check 489 */ 490 static inline bool core_mmu_is_dynamic_vaspace(struct tee_mmap_region *mm) 491 { 492 return mm->type == MEM_AREA_RES_VASPACE || 493 mm->type == MEM_AREA_SHM_VASPACE; 494 } 495 496 /* 497 * core_mmu_map_pages() - map list of pages at given virtual address 498 * @vstart: Virtual address where mapping begins 499 * @pages: Array of page addresses 500 * @num_pages: Number of pages 501 * @memtype: Type of memmory to be mapped 502 * 503 * Note: This function asserts that pages are not mapped executeable for 504 * kernel (privileged) mode. 505 * 506 * @returns: TEE_SUCCESS on success, TEE_ERROR_XXX on error 507 */ 508 TEE_Result core_mmu_map_pages(vaddr_t vstart, paddr_t *pages, size_t num_pages, 509 enum teecore_memtypes memtype); 510 511 /* 512 * core_mmu_map_contiguous_pages() - map range of pages at given virtual address 513 * @vstart: Virtual address where mapping begins 514 * @pstart: Physical address of the first page 515 * @num_pages: Number of pages 516 * @memtype: Type of memmory to be mapped 517 * 518 * Note: This function asserts that pages are not mapped executeable for 519 * kernel (privileged) mode. 520 * 521 * @returns: TEE_SUCCESS on success, TEE_ERROR_XXX on error 522 */ 523 TEE_Result core_mmu_map_contiguous_pages(vaddr_t vstart, paddr_t pstart, 524 size_t num_pages, 525 enum teecore_memtypes memtype); 526 527 /* 528 * core_mmu_unmap_pages() - remove mapping at given virtual address 529 * @vstart: Virtual address where mapping begins 530 * @num_pages: Number of pages to unmap 531 */ 532 void core_mmu_unmap_pages(vaddr_t vstart, size_t num_pages); 533 534 /* 535 * core_mmu_user_mapping_is_active() - Report if user mapping is active 536 * @returns true if a user VA space is active, false if user VA space is 537 * inactive. 538 */ 539 bool core_mmu_user_mapping_is_active(void); 540 541 /* 542 * core_mmu_mattr_is_ok() - Check that supplied mem attributes can be used 543 * @returns true if the attributes can be used, false if not. 544 */ 545 bool core_mmu_mattr_is_ok(uint32_t mattr); 546 547 void core_mmu_get_mem_by_type(enum teecore_memtypes type, vaddr_t *s, 548 vaddr_t *e); 549 550 enum teecore_memtypes core_mmu_get_type_by_pa(paddr_t pa); 551 552 /* routines to retreive shared mem configuration */ 553 static inline bool core_mmu_is_shm_cached(void) 554 { 555 return mattr_is_cached(core_mmu_type_to_attr(MEM_AREA_NSEC_SHM)); 556 } 557 558 TEE_Result core_mmu_remove_mapping(enum teecore_memtypes type, void *addr, 559 size_t len); 560 void *core_mmu_add_mapping(enum teecore_memtypes type, paddr_t addr, 561 size_t len); 562 563 /* 564 * core_mmu_find_mapping_exclusive() - Find mapping of specified type and 565 * length. If more than one mapping of 566 * specified type is present, NULL will be 567 * returned. 568 * @type: memory type 569 * @len: length in bytes 570 */ 571 struct tee_mmap_region * 572 core_mmu_find_mapping_exclusive(enum teecore_memtypes type, size_t len); 573 574 /* 575 * tlbi_va_range() - Invalidate TLB for virtual address range 576 * @va: start virtual address, must be a multiple of @granule 577 * @len: length in bytes of range, must be a multiple of @granule 578 * @granule: granularity of mapping, supported values are 579 * CORE_MMU_PGDIR_SIZE or SMALL_PAGE_SIZE. This value must 580 * match the actual mappings. 581 */ 582 void tlbi_va_range(vaddr_t va, size_t len, size_t granule); 583 584 /* 585 * tlbi_va_range_asid() - Invalidate TLB for virtual address range for 586 * a specific ASID 587 * @va: start virtual address, must be a multiple of @granule 588 * @len: length in bytes of range, must be a multiple of @granule 589 * @granule: granularity of mapping, supported values are 590 * CORE_MMU_PGDIR_SIZE or SMALL_PAGE_SIZE. This value must 591 * match the actual mappings. 592 * @asid: Address space identifier 593 */ 594 void tlbi_va_range_asid(vaddr_t va, size_t len, size_t granule, uint32_t asid); 595 596 /* Check cpu mmu enabled or not */ 597 bool cpu_mmu_enabled(void); 598 599 #ifdef CFG_CORE_DYN_SHM 600 /* 601 * Check if platform defines nsec DDR range(s). 602 * Static SHM (MEM_AREA_NSEC_SHM) is not covered by this API as it is 603 * always present. 604 */ 605 bool core_mmu_nsec_ddr_is_defined(void); 606 607 void core_mmu_set_discovered_nsec_ddr(struct core_mmu_phys_mem *start, 608 size_t nelems); 609 #endif 610 611 /* Initialize MMU partition */ 612 void core_init_mmu_prtn(struct mmu_partition *prtn, struct tee_mmap_region *mm); 613 614 unsigned int asid_alloc(void); 615 void asid_free(unsigned int asid); 616 617 #ifdef CFG_SECURE_DATA_PATH 618 /* Alloc and fill SDP memory objects table - table is NULL terminated */ 619 struct mobj **core_sdp_mem_create_mobjs(void); 620 #endif 621 622 #ifdef CFG_NS_VIRTUALIZATION 623 size_t core_mmu_get_total_pages_size(void); 624 struct mmu_partition *core_alloc_mmu_prtn(void *tables); 625 void core_free_mmu_prtn(struct mmu_partition *prtn); 626 void core_mmu_set_prtn(struct mmu_partition *prtn); 627 void core_mmu_set_default_prtn(void); 628 void core_mmu_set_default_prtn_tbl(void); 629 #endif 630 631 void core_mmu_init_virtualization(void); 632 633 /* init some allocation pools */ 634 void core_mmu_init_ta_ram(void); 635 636 void core_init_mmu(struct tee_mmap_region *mm); 637 638 void core_mmu_set_info_table(struct core_mmu_table_info *tbl_info, 639 unsigned int level, vaddr_t va_base, void *table); 640 void core_mmu_populate_user_map(struct core_mmu_table_info *dir_info, 641 struct user_mode_ctx *uctx); 642 void core_mmu_map_region(struct mmu_partition *prtn, 643 struct tee_mmap_region *mm); 644 645 bool arch_va2pa_helper(void *va, paddr_t *pa); 646 647 static inline bool core_mmap_is_end_of_table(const struct tee_mmap_region *mm) 648 { 649 return mm->type == MEM_AREA_END; 650 } 651 652 static inline bool core_mmu_check_end_pa(paddr_t pa, size_t len) 653 { 654 paddr_t end_pa = 0; 655 656 if (ADD_OVERFLOW(pa, len - 1, &end_pa)) 657 return false; 658 return core_mmu_check_max_pa(end_pa); 659 } 660 661 /* 662 * core_mmu_set_secure_memory() - set physical secure memory range 663 * @base: base address of secure memory 664 * @size: size of secure memory 665 * 666 * The physical secure memory range is not known in advance when OP-TEE is 667 * relocatable, this information must be supplied once during boot before 668 * the translation tables can be initialized and the MMU enabled. 669 */ 670 void core_mmu_set_secure_memory(paddr_t base, size_t size); 671 672 /* 673 * core_mmu_get_secure_memory() - get physical secure memory range 674 * @base: base address of secure memory 675 * @size: size of secure memory 676 * 677 * The physical secure memory range returned covers at least the memory 678 * range used by OP-TEE Core, but may cover more memory depending on the 679 * configuration. 680 */ 681 void core_mmu_get_secure_memory(paddr_t *base, paddr_size_t *size); 682 683 /* 684 * core_mmu_get_ta_range() - get physical memory range reserved for TAs 685 * @base: [out] range base address ref or NULL 686 * @size: [out] range size ref or NULL 687 */ 688 void core_mmu_get_ta_range(paddr_t *base, size_t *size); 689 690 #endif /*__ASSEMBLER__*/ 691 692 #endif /* CORE_MMU_H */ 693